參數(shù)資料
型號： PTPS659104A1RSL
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 20/89頁
文件大小： 941K
代理商： PTPS659104A1RSL
PRODUCTPREVIEW
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
VDAC AND VPLL LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 2.5 V, IOUT = IOUTmax, T = 25°C
DC load regulation
On mode, IOUT = IOUTmax to 0
10
mV
DC line regulation
On mode, VIN = VINmin to VINmax @ IOUT = IOUTmax
1
mV
On mode, VIN = 3.8v, IOUT = 0.1 × IOUTmax to 0.9 ×
Transient load regulation
6
mV
IOUTmax in 5 s
And IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 s
Transient line regulation
On mode, VIN = VINmin + 0.5 V to VINmin in 30 s
0.5
mV
And VIN = VINmin to VINmin + 0.5 V in 30 s, IOUT =
IOUTmax/2
Turn-on time
IOUT = 0, @ VOUT = 0.1 V up to VOUTmin
100
s
Turn-on inrush current
300
mA
VIN = VINDC + 100 mVpp tone, VINDC+ = 3.8 V, IOUT =
Ripple rejection
IOUTmax/2
f = 217 Hz
70
dB
f = 50 kHz
40
VPLL internal resistance
LDO off
500
k
Ω
Ground current
On mode, IOUT = 0
60
On mode, IOUT = IOUTmax
1600
A
Low-power mode
12
Off mode
1
SWITCH-ON/-OFF SEQUENCES AND TIMING
BOOT1 = 0, BOOT0 = 0
Table 2 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 2.
Table 2. Fixed Boot Mode: 00
TPS65910
Register
Bit
Description
Boot 00
VDD1_OP_REG
SEL
VDD1 voltage level selection for boot
1.2 V
VDD1_REG
VGAIN_SEL
VDD1 Gain selection, x1 or x2
x1
EEPROM
VDD1 time slot selection
3
DCDCCTRL_REG
VDD1_PSKIP
VDD1 pulse skip mode enable
skip enabled
VDD2_OP_REG/VDD2_SR_REG
SEL
VDD2 voltage level selection for boot
1.1 V
VDD2_REG
VGAIN_SEL
VDD2 Gain selection, x1 or x3
x3
EEPROM
VDD2 time slot selection
2
DCDCCTRL_REG
VDD2_PSKIP
VDD2 pulse skip mode enable
skip enabled
VIO_REG
SEL
VIO voltage selection
1.8 V
EEPROM
VIO time slot selection
1
DCDCCTRL_REG
VIO_PSKIP
VIO pulse skip mode enable
skip enabled
EEPROM
VDD3 time slot
OFF
VDIG1_REG
SEL
LDO voltage selection
1.2 V
EEPROM
LDO time slot
OFF
VDIG2_REG
SEL
LDO voltage selection
1.0 V
EEPROM
LDO time slot
OFF
VDAC_REG
SEL
LDO voltage selection
1.8 V
EEPROM
LDO time slot
5
Copyright 2010, Texas Instruments Incorporated
27
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