參數(shù)資料
型號(hào)： PTH04000WAST
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源模塊
英文描述： 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
封裝： DIP-6
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 727K
代理商： PTH04000WAST
www.ti.com
ELECTRICAL CHARACTERISTICS
SLTS247B – JUNE 2005 – REVISED OCTOBER 2007
at 25
°C free-air temperature, V
I = 5 V, VO = 3.3 V, IO = IO(Max), CI = 47 F (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IO
Output current
TA = 25°C, natural convection
0
3 (1)
A
VI
Input voltage range
Over IO range
3 (2)
5.5
V
VO(TOL)
Set-point voltage tolerance
TA = 25°C
±2 (3)
%VO
Temperature variation
–40
°C ≤ T
A ≤ 85°C
±0.5
%VO
Line regulation
Over VI range
±1
mV
Load regulation
Over IO range
±5
mV
Includes set-point, line, load,
Total output voltage variation
±3(3)
%VO
–40
°C ≤ T
A ≤ 85°C
VI ≥ 4.5 V
0.9
3.6
VO(ADJ)
Output voltage adjust range
V
VI < 4.5 V
0.9
VI – 1.1
(2)
TA = 25C, IO = 2 A
RSET = 475 , VO = 3.3 V
(2)
92%
RSET = 2.32 k, VO = 2.5 V
(2)
89%
η
Efficiency
RSET = 6.65 k, VO = 1.8 V
86%
RSET = 11.5 k, VO = 1.5 V
84%
RSET = 26.1 k, VO = 1.2 V
82%
RSET = 84.5 k, VO = 1 V
78%
Output voltage ripple
20 MHz bandwith
10
mVPP
Overcurrent threshold
Reset, followed by autorecovery
7
A
1 A/s load step from 50% to 100% IOmax,
CO = 47 F
Transient response
Recovery time
70
s
VO over/undershoot
100
mV
IIL track
Track Input Current (pin 2)
Pin to GND
–130
A
dVtrack/dt
Track Slew Rate Capability
CO ≤ CO(max)
1
V/ms
VI = increasing
2.95
3
UVLO
Undervoltage lockout
V
VI = decreasing
2.7
2.8
Input high voltage (VIH)
VI – 0.5
Open (4)
V
Inhibit control (pin 4)
Input low voltage (VIL)
–0.2
0.6
Input low current (IIL)
10
A
II (STBY)
Input standby current
Inhibit (pin 4) to GND, Track (pin 2) open
1
mA
FS
Switching frequency
Over VI and IO ranges
700
kHz
External input capacitance
Ceramic type (C1)
47 (5)
F
Ceramic type (C2)
0 (6)
150
F
External output capacitance (6)
Nonceramic type (C3)
47 (6)
560 (7)
Equivalent series resistance (nonceramic)
4 (8)
m
Per Telcordia SR-332, 50% stress,
MTBF
Calculated reliability
15
106 Hr
TA = 40C, ground benign
(1)
See SOA temperature derating curves to identify maximum output current at higher ambient temperatures.
(2)
The minimum input voltage is 3 V or (VO + 1.1) V, whichever is greater. A 5-V input bus is recommended for output voltages higher than
2 V.
(3)
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with 100 ppm/
°C or better temperature stability.
(4)
This control pin has an internal pullup to the input voltage VI. Do not tie the inhibit pin to VI or to another module's inhibit pin. If it is left
open circuit, the module operates when input power is applied. A small low-leakage (< 100 nA) MOSFET is recommended for control.
See the application section for further guidance.
(5)
An external 47-F ceramic capacitor is required across the input (VI and GND) for proper operation. Locate the capacitor close to the
module.
(6)
An external output capacitor is not required for basic operation. Additional capacitance at the load improves the transient response.
(7)
This is the calculated maximum capacitance. The minimum ESR limitation often results in a lower value. See the capacitor application
information for further guidance.
(8)
This is the minimum ESR for all the electrolytic (nonceramic) capacitance. Use 7 m
as the minimum when calculating the total
equivalent series resistance (ESR) using the max-ESR values specified by the capacitor manufacturer.
Copyright 2005–2007, Texas Instruments Incorporated
3
Product Folder Link(s): PTH04000W
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