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參數(shù)資料
| 型號(hào)： | PTD08D210WACT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-22 |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大?。?/td> | 480K |
| 代理商： | PTD08D210WACT |
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V
I
V
I
1
2
3
4
5
6
7
8
9
10
11
PGND
PWM-B
PGND
PWM-A
22
21
20
19
18
17
16
15
14
13
12
V
O-A
SRE-A
PGND
T
SENSE
I
SENSE
-A
V
O-B
SRE-B
I
SENSE
-B
FF-B
V
O-B
FF-A
AGND
V
O-A
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Thermal
Pad
TOP VIEW
BOTTOM VIEW
www.ti.com
SLTS295B – DECEMBER 2009 – REVISED DECEMBER 2010
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
VI
1, 2
The positive input voltage power node to the module, which is referenced to common GND.
3, 8, 9, 19,
PGND
The common ground connection for the VI and VO power connections.
20
VOA
21, 22
The regulated positive power A output with respect to GND.
VOB
10, 11
The regulated positive power B output with respect to GND.
ISENSE-A
14
Current sense A output. The voltage level on this pin represents the average output current of the module.
ISENSE-B
6
Current sense B output. The voltage level on this pin represents the average output current of the module.
This is the PWM A input pin. It is a high impedance digital input that accepts 3.3-V or 5-V logic level signals up to
PWM-A
18
1 MHz.
This is the PWM B input pin. It is a high impedance digital input that accepts 3.3-V or 5-V logic level signals up to
PWM-B
4
1 MHz.
Current limit fault flag A. The Fault signal is a 3.3-V digital output which is latched high after an over-current
FF-A
15
condition. The Fault is reset after a complete PWM cycle without an over-current condition (falling edge of the
PWM).
Current limit fault flag A. The Fault signal is a 3.3-V digital output which is latched high after an over-current
FF-B
7
condition. The Fault is reset after a complete PWM cycle without an over-current condition (falling edge of the
PWM).
Synchronous Rectifier Enable A. This pin is a high impedance digital input. A 3.3 V or 5 V logic level signals is used
SRE-A
17
to enable the synchronous rectifier switch. When this signal is high, the module will source and sink output current.
When this signal is low, the module will only source current.
Synchronous Rectifier Enable B. This pin is a high impedance digital input. A 3.3 V or 5 V logic level signals is used
SRE-B
5
to enable the synchronous rectifier switch. When this signal is high, the module will source and sink output current.
When this signal is low, the module will only source current.
AGND
12, 13
Analog ground return. It is the 0 Vdc reference for the control inputs.
TSENSE
16
Temperature sense output. The voltage level on this pin represents the temperature of the module.
This pad is electrically connected to PGND and is the primary thermal conduction cooling path for the module. This
Thermal
pad should be soldered to a grounded copper pad on the host board. For optimum cooling performance, the
Pad
grounded copper pad should also be tied with multiple vias to the host board internal ground plane. See the Land
Pattern drawing for package EFS for recommended pad dimensions.
XX
Copyright 2009–2010, Texas Instruments Incorporated
5
Product Folder Link(s): PTD08D210W
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