參數(shù)資料
型號(hào): PT7C4511
英文描述: PLL Clock Multiplier?
中文描述: PLL時(shí)鐘倍頻?
文件頁數(shù): 1/7頁
文件大?。?/td> 164K
代理商: PT7C4511
Data Sheet
PT7C4501/4501A Frequency Multiplier
PT0139(12/03)
Ver:0
1
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Features
Low cost frequency multiplier
Zero ppm multiplication error
Input crystal frequency of 5 - 30 MHz
Input clock frequency of 4 - 50 MHz
Output clock frequencies up to 180 MHz
Cycle to cycle jitter less than 150ps (70~180MHz)
Duty cycle of 45/55 up to 180 MHz
9 selectable frequencies controlled by S0, S1 pins
Operating voltages of 3.0 to 5.5V
Tri-state output for board level testing
General
The PT7C4501/4501A is a high performance frequency
multiplier, which integrates Analog Phase Lock Loop
techniques.
The PT7C4501/4501A is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most
electronic systems, clock multiplier and frequency
translation.
Using Phase-Locked-Loop (PLL) techniques, the
device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to
180 MHz.
The complex Logic divider is the ability to generate
nine different popular multiplication factors, allowing
one chip to output many common frequencies.
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken low.
This product is intended for clock generation and
frequency translation with low output jitter (variation
in the output period)
Block Diagram
PLL Clock Synthesis
and
Control Circuit
Crystal
Oscillator
S0
S1
X2
CLK
V
CC
GND
X1/ICLK
Output
Buffer
OE
Part Number
Package
PT7C4501W
8 - Pin SOIC
PT7C4501AW
8 - Pin SOIC
Ordering Information
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