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Slave Address

The I

2

C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,

slave addresses are allocated to each device.

All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device

responds to this communication only when the specified slave address it has received matches its own slave address.

Slave addresses have a fixed length of 7 bits. See table for the details.

An R/W bit is added to each 7-bit slave address during 8-bit transfers.

Table

Slave address

Operation

Transfer data

bit 7

bit 6

bit 5

Read

D1 h

Write

D0 h

I

2

C Bus’s Basic Transfer Format

1)

Write via I

2

C bus

PT0205(02/07)

Ver: 1

17

Data Sheet

PT7C4337

Real-time Clock Module (I

2

C Bus)

R / W bit

bit 0

1 (= Read)

0 (= Write)

bit 4

bit 3

bit 2

bit 1

1

1

0

1

0

0

0

S

Start indication

P

Stop indication

Sr

Restart indication

A

RTC Acknowledge

A

Master Acknowledge

Slave address (7 bits)

1

1

0

1

0

0

0

0

write

Addr. setting

Slave address + write specification

Address

Specifies the write start address.

A

bit

7

6

5

4

3

2

1

0

bit

bit

bit

bit

bit

bit

bit

A

P

Write data

S

A

A

C

K

A

C

K

A

C

K

Start

Stop