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I

2

C Bus Interface

Overview of I

2

C-BUS

The I

2

C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination

of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and

stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data

transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the

data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per

clock pulse. The I

2

C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a

chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its

slave address matches the slave address in the received data.

System Configuration

All ports connected to the I

2

C bus must be either open drain or open collector ports in order to enable AND connections to

multiple devices.

SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high

level when the bus is released (when communication is not being performed).

Fig 1.

System configuration

PT0205(02/07)

Ver: 1

14

Data Sheet

PT7C4337

Real-time Clock Module (I

2

C Bus)

Master

MCU

Slave

RTC

Other Peripheral

Device

Vcc

SDA

SCL

Note: When there is only one master, the MCU is ready for driving SCL to "H" and R

P

of SCL may not required.

R

P

R

P