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8
PT0011(09/02)
Ver:3
Data Sheet
PT7A8980/8980L Digital Switch
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Normal Mode
The PT7A8980/8980L mainly has two modes of operation,
Normal Mode and Message Mode. In Normal Operation Mode,
data on the ST-BUS output comes from the ST-BUS input.
The microprocessor can decide which channel inputs and
which channel outputs. It establishes switching connections
between input channels and output channels by programming
the Connection Memory Low. Note that the contents of Con-
nection Memory Low locations are used to address the Data
Memory locations associated with the input channels (see
Figure 5 and Table 6). This relationship allows an input chan-
nel to be switched to its destined output channel (refer to
Input and Output Control section).
Message Mode
In Message mode, the contents of the Connection Memory
Low location associated with the output channel are driven
out directly on this output channel. The processor can put out
specific message to any output channel by writing the mes-
sage data to its Connection Memory Low location.
An output channel can be put into Message Mode in two
ways, i.e.,
1) Bit 6 of the Control Register is set 1, or
2) Bit 2 of the Connection Memory High location associated
with the channel is set 1.
If Bit 6 of the Control Register is 1, all 256 output channels
are in Message Mode no matter what value of Bit 2 in each
Connection Memory High location is. If Bit 2 of the associ-
ated Connection Memory High location is 1 and the Bit 6 of
the Control Register is 0, only this output channel is in Mes-
sage Mode. Therefore, the Control Register overrides the
Connection Memory High in setting the channels to Message
Mode.
When a ST-BUS output channel is in Message Mode, the data
byte in its connection Memory Low location is output on the
corresponding channel slot of output data stream.
ST-BUS Output High Impedance
If the ODE pin of the chip is low, all the ST-BUS output pins
will be in high impedance state regardless of operation mode
of PT7A8980/8980L.
Each output channel can also be set in high impedance re-
spectively by writing a 0 to the Output Enable bit (Bit 0) of
the corresponding Connection Memory High location (see
Figure 4 and Table 5 ). However, this is possible only when the
ODE pin is high and Bit 6 in the Control memory High loca-
tion is 0. Otherwise, the Output Enable bit has no effect on the
output channel. This feature is useful when constructing
switching matrices.
CSTo Output
the CSTo Bit (Bit 1) of each Connection Memory High loca-
tion (see Figure 4 and Table 5) is output on the CSTo pin
every frame. The order of these bits on the CSTo output pin is
as follows.
All the 8 CSTo Bits corresponding to the same channel num-
bers on the 8 data streams STo0~7 are grouped together for
output via the CSTo pin in one-channel time-slot . The CSTo
Bit for data stream STo0 always comes out first within the
time-slot, then the bits STo1, STo2,..., STo7.
To account for the possible delay in the external control cir-
cuitry, each group of the CSTo Bits is output in one-channel
time-slot before data on the corresponding channel comes out
to the ST-BUS data stream (see Figure 13). The CSTo Bits for
channel 0, for example, are output on the CSTo during the
channel 31 time-slot of the last frame, and CSTo Bits for chan-
nel 1 are output during the channel 0 time-slot of the same
frame.