PSB 2115
PSF 2115
Functional Description
Semiconductor Group
40
11.97
Note: In DMA-mode the command XREP, XTF has to be written to CMDRB.
2.1.10
If data transfer from system memory to the IPAC is done by DMA (DMA bit in XBCH set),
the number of bytes to be transmitted is usually defined via the Transmit Byte Count
registers (XBCH, XBCL : bits XBC11 ... XBC0).
Setting the Transmit Continuously“ (XC) bit in XBCH, however, the byte count value is
ignored and the DMA interface of the IPAC will continuously request for transmit data
any time 64 bytes can be stored in the XFIFOB.
Continuous Transmission (DMA Mode only)
This feature can be used e.g. to
continuously transmit voice or data onto a PCM highway, or to
transmit frames exceeding the byte count programmable via XBCH, XBCL (frames
with more than 4095 bytes).
Note: If the XC bit is reset during continuous transmission, the transmit byte count
becomes valid again, and the IPAC will request the amount of DMA transfers
programmed via XBC11 ... XBC0. Otherwise the continuous transmission is
stopped when a data underrun condition occurs in the XFIFOB, i.e. the DMA
controller does not transfer further data to the IPAC. In this case continuous ’1’-s
(idle), without appending a CRC, are transmitted.
2.1.11
The IPAC offers the possibility to supervise the maximum length of received frames and
to terminate data reception in case this length is exceeded.
This feature is controlled via the special Receive Length Check Register (RLCR).
The function is enabled by setting the RC (Receive Check) bit in RLCR and
programming the maximum frame length via bits RL5 … RL0
1)
.
According to the value written to RL5 … RL0, the maximum receive length can be
adjusted in multiples of 64-byte blocks as follows:
Receive Length Check Feature
All frames exceeding this length are treated as if they have been aborted from the
opposite station, i.e. the CPU is informed via a
1)
The frame length includes all bytes which are stored in the RFIFOB.
MAX. LENGTH = (RL + 1)
×
64.