參數(shù)資料
型號: PSD935F3V-15B81
廠商: 意法半導體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 4/91頁
文件大?。?/td> 488K
代理商: PSD935F3V-15B81
PSD935G2
PSD9XX Family
J
A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80188, 80C251
Motorola 68HC11 and 68HC16
Philips 8031 and 80C51XA
Zilog Z80, Z8 and Z180
Infineon C500 family
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4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
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Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash
concurrently.
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64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
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General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
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Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
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52 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
I/O ports may be configured as open-drain outputs.
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Standby current as low as 50 μA for 5 V devices.
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Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
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Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
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Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode.
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Erase/Write cycles:
Flash memory – 100,000 minimum
PLD – 1,000 minimum
2.0
Key Features
3
3.0 PSD9XX
Series
Part #
Flash
Main
Memory
Kbit
8 Sectors
Flash
Serial ISP
JTAG/ISP
Port
Boot
Memory
Kbit
(4 Sectors)
PSD9XX
Series
I/O
Pins
PLD
Inputs Macrocells Macrocells Outputs
Input
Output
PLD
SRAM
Kbit
Supply
Voltage
Device
PSD935G2
PSD913G2
PSD934F2
52
27
27
66
57
57
24
19
19
Yes
Yes
Yes
4096
1024
2048
256
256
256
64
16
64
5V
5V
5V
PSD9XX
Table 1. PSD9XX Product Matrix
相關PDF資料
PDF描述
PSD935F3V-15B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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