參數(shù)資料
型號(hào): PSD9343V90MIT
廠商: 意法半導(dǎo)體
英文描述: Economy Primary Side Controller 8-TSSOP -40 to 85
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 72/110頁
文件大?。?/td> 1737K
代理商: PSD9343V90MIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
72/110
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD:
DC Electrical Specification
AC Timing Specification
PLD Timing
Combinatorial Timing
Synchronous Clock Mode
Asynchronous Clock Mode
Input Macrocell Timing
MCU Timing
READ Timing
WRITE Timing
Peripheral Mode Timing
Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo Bit is ’0.’
The AC power component gives the PLD,
Flash memory, and SRAM mA/MHz
specification. Figures
35
and
36
show the PLD
mA/MHz as a function of the number of
Product Terms (PT) used.
In the PLD timing parameters, add the
required delay when Turbo Bit is ’0.’
Figure 35. PLD I
CC
/Frequency Consumption (5V range)
110
Figure 36. PLD I
CC
/Frequency Consumption (3V range)
0
10
20
30
40
60
70
80
90
100
V
CC
= 5V
TURBO ON (100%)
50
0
10
15
5
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
I
C
TURBO ON (25%)
TURBOOFF
TURBO OFF
PT 100%
PT 25%
AI02894
0
10
20
30
40
50
60
V
CC
= 3V
0
10
15
5
20
25
I
C
TURBO ON (100%)
TURBO ON (25%)
TURBOOFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI03100
相關(guān)PDF資料
PDF描述
PSD9343V90MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934412JIT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412JT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412MIT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412MT Economy Primary Side Controller 8-MSOP -40 to 85
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