參數(shù)資料
型號: PSD9343V90MIT
廠商: 意法半導(dǎo)體
英文描述: Economy Primary Side Controller 8-TSSOP -40 to 85
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 49/110頁
文件大?。?/td> 1737K
代理商: PSD9343V90MIT
49/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C51XA
The Philips 80C51XA MCU family supports an 8-
or 16-bit multiplexed bus that can have burst cy-
cles. Address bits (A3-A0) are not multiplexed,
while (A19-A4) are multiplexed with data bits
(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)
are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure
24
).
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from ad-
dress A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
31
33
36
24
25
26
27
28
29
30
2
3
4
5
43
42
41
40
39
38
37
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A18
A19
A17
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A16
A17
A18
A19
A15
TXD1
T2EX
T2
T0
RST
INT0
INT1
EA/WAIT
BUSW
A1
A2
A3
A0/WRH
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
PSEN
RD
WRL
ALE
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PSEN
RD
WR
ALE
32
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
7
9
8
16
XTAL1
XTAL2
RXD0
TXD0
RXD1
21
20
11
13
6
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
A0
A1
A2
A3
80C51XA
PSD
RESET
RESET
35
17
14
15
10
AI02883C
相關(guān)PDF資料
PDF描述
PSD9343V90MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934412JIT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412JT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412MIT Economy Primary Side Controller 8-SOIC -40 to 85
PSD934412MT Economy Primary Side Controller 8-MSOP -40 to 85
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