參數(shù)資料
型號: PSD854F2A-90MT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù): 12/128頁
文件大?。?/td> 1045K
代理商: PSD854F2A-90MT
PSD8XXFX
AC/DC parameters
Doc ID 7833 Rev 7
109/128
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
27
30
38
ns
tDVMV
Data valid to port output valid
using macrocell register
Preset/Clear
42
55
65
ns
tAVPV
Address input valid to address
output delay
(5)
20
25
30
ns
tWLMV
WR valid to port output valid using
macrocell register Preset/Clear
48
55
65
ns
1.
Any input used to select an internal PSD function.
2.
WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
3.
tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
4.
Assuming WRITE is active before data becomes valid.
5.
In multiplexed mode, latched address generated from ADIO delay to address output on any port.
6.
Assuming data is stable before active WRITE signal.
Table 58.
WRITE timing (5 V devices) (continued)
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min
Max Min Max
Table 59.
WRITE timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Unit
MinMax MinMax
MinMax
tLVLX
ALE or AS pulse width
26
30
tAVLX
Address setup time
(1)
910
12
ns
tLXAX
Address hold time
912
14
ns
tAVWL
Address valid to Leading
Edge of WR
(1)(2)
17
20
25
ns
tSLWL
CS valid to Leading Edge of WR
17
20
25
ns
tDVWH
WR data setup time
45
50
ns
tWHDX
WR data hold time
7
8
10
ns
tWLWH
WR pulse width
46
48
53
ns
tWHAX1
Trailing edge of WR to address invalid
10
12
17
ns
tWHAX2
Trailing edge of WR to DPLD address
invalid
(2)(3)
00
0
ns
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
33
35
40
ns
tDVMV
Data valid to port output valid
using macrocell register Preset/Clear
(2)(4)
70
80
ns
相關PDF資料
PDF描述
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
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PSD854F2V-12MI 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC