參數(shù)資料
型號： PSD854F2A-90MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： ROHS COMPLIANT, PLASTIC, QFP-52
文件頁數(shù)： 112/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90MT
Power management
PSD8XXFX
Doc ID 7833 Rev 7
17.5
PSD Chip Select input (CSI, PD2)
PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When
low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O
blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input
(CSI, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power
consumption. However, the PLD and I/O signals remain operational when PSD Chip Select
input (CSI, PD2) is high.
There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 62
17.6
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting Bits 4 or 5 to a 1 in PMMR0.
17.7
Input control signals
The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2,
Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These
control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of
them are not being used as part of the PLD logic equation, these control signals should be
disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits
2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 33.
APD counter operation
APD Enable
bit
ALE PD
polarity
ALE level
APD counter
0
X
Not counting
1
X
Pulsing
Not counting
1
Counting (generates PDN after 15 clocks)
1
0
Counting (generates PDN after 15 clocks)
相關(guān)PDF資料
PDF描述
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
PSH665-FREQ-OUT1 VCXO, SINE OUTPUT, 465 MHz - 865 MHz
PSM3-022K 1 ELEMENT, 0.022 uH, GENERAL PURPOSE INDUCTOR, SMD
PSM3-068K 1 ELEMENT, 0.068 uH, GENERAL PURPOSE INDUCTOR, SMD
PSM3-120K 1 ELEMENT, 0.12 uH, GENERAL PURPOSE INDUCTOR, SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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