參數(shù)資料
    

    


    


    
型號(hào)：
PSD835G3V-A-15B81I

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

    

    
文件頁數(shù)：
39/110頁

    

    
文件大?。?/td>
570K

    

    
代理商：
PSD835G3V-A-15B81I


    

    

    

	
    
    
    

    
    
	
    PSD8XX Family 
    PSD835G2
    38
    The 
    PSD835G2
    Functional
    Blocks
    (cont.)
    9.2.2.1   Output Micro
    Cell
    Eight of the Output Micro
    Cells are connected to Port A pins are named as McellA0-7. 
    The other eight Micro
    Cells are connected to Port B pins are named as McellB0-7. 
    Maximum
    Borrowed
    Product
    Terms
    Native
    Product
    Terms
    Data Bit for
    Loading or
    Reading
    Output
    Micro
    Cell
    Port
    Assignment
    McellA0
    Port A0
    3
    6
    D0
    McellA1
    McellA2
    McellA3
    McellA4
    McellA5
    McellA6
    McellA7
    McellB0
    McellB1
    McellB2
    McellB3
    McellB4
    McellB5
    McellB6
    McellB7
    Port A1
    Port A2
    Port A3
    Port A4
    Port A5
    Port A6
    Port A7
    Port B0
    Port B1
    Port B2
    Port B3
    Port B4
    Port B5
    Port B6
    Port B7
    3
    3
    3
    3
    3
    3
    3
    4
    4
    4
    4
    4
    4
    4
    4
    6
    6
    6
    6
    6
    6
    6
    5
    5
    5
    5
    6
    6
    6
    6
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    D0
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    Table 13.  Output Micro
    Cell Port and Data Bit Assignments
    The Output Micro
    Cell (OMC) architecture is shown in Figure 13. As shown in the figure,
    there are native product terms available from the AND array, and borrowed product terms
    available (if unused) from other OMCs. The polarity of the product term is controlled by the
    XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
    combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
    outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
    array inputs.
    The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDsoft 
    program. The flip-flop
    ’
    s clock, preset, and clear inputs may be driven from a product term 
    of the AND array. Alternatively, the external CLKIN signal can be used for the clock input
    to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
    clear are active-high inputs. Each clear input can use up to two product terms.  
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD835G3V-A-15J
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-A-15JI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-A-15M
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-A-15MI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-A-15U
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    

    

    


    


    

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