參數資料
型號： PSD835G3V-A-15B81I
廠商： 意法半導體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數： 36/110頁
文件大?。?/td> 570K
代理商： PSD835G3V-A-15B81I
PSD835G2
PSD8XX Family
35
The
PSD835G2
Functional
Blocks
(cont.)
Each of the two PLDs has unique characteristics suited for its applications They are
described in the following sections.
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 11, is used for decoding the address for internal and external
components. The DPLD can generate the following decode signals:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the Flash Boot memory
(three product terms each)
1 internal SRAM select signal (three product terms)
1 internal CSIOP (PSD configuration register) select signal
1 JTAG select signal (enables JTAG-ISP on Port E)
2 internal peripheral select signals (peripheral I/O mode).
9.2.2 Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters
and shift registers, system mailboxes, handshaking protocols, state machines, and
random logic. The CPLD can also be used to generate 8 external chip selects, routed to
Port C or F. Although external chip selects can be produced by any Output Micro
Cell,
these eight external chip selects on Port C or F do not consume any Output Micro
Cells.
As shown in Figure 10, the CPLD has the following blocks:
24 Input Micro
Cells (IMCs)
16 Output Micro
Cells (OMCs)
Product Term Allocator
AND array capable of generating up to 196 product terms
Four I/O ports.
Each of the blocks are described in the subsections that follow.
The Input and Output Micro
Cells are connected to the PSD835G2 internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro
Cells or read data from both the Input and Output
Micro
Cells. This feature allows efficient implementation of system logic and eliminates
the need to connect the data bus to the AND logic array as required in most standard PLD
macrocell architectures.
相關PDF資料
PDF描述
PSD835G3V-A-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-A-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-A-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-A-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-A-15U Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關代理商/技術參數
參數描述
PSD853F2-70J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD853F2-70M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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