參數(shù)資料
型號(hào)： PSD834F2V
英文描述： Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位雙路閃速存儲(chǔ)器和64K位靜態(tài)RAM,閃速PSD,3.3V電源,用于8位MCU.)
中文描述： 閃光私營(yíng)部門，3.3V電源，為8位微控制器2兆256千位雙閃存和64千位的SRAM（200萬(wàn)位256K位雙路閃速存儲(chǔ)器和64K的位靜態(tài)內(nèi)存，閃速私營(yíng)部門，3.3V的電源，用于8位微控制器。）
文件頁(yè)數(shù)： 18/89頁(yè)
文件大小： 522K
代理商： PSD834F2V
PSD834F2V
18/89
“Programming Flash Memory”, onpage 19, for de-
tails.
Table 8. Status Bit
Note: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3are active High.
Data Polling Flag (DQ7).
When erasing or pro-
gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the complement of the bit being
entered for programming/writing on the DQ7 bit.
Once the Program instruction or the Write opera-
tion is completed, the true logic value is read on
the Data Polling Flag (DQ7) bit (in a Read opera-
tion).
I
Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
I
During an Erase cycle, the Data Polling Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed(it is a 1 after erasing).
I
If the byte to be programmed is in a protected
Flash memory sector, the instruction is ignored.
I
If all theFlash memory sectors to be erased are
protected, the Data Polling Flag (DQ7) bit is
reset to 0 for about 100
μ
s, and then returns to
the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6).
The PSD offers another way
for determining when the Flash memory Program
cycle is completed. During the internal Write oper-
ation and when either the FS0-FS7 or CSBOOT0-
CSBOOT3 is true, the Toggle Flag (DQ6) bit tog-
gles from 0 to 1 and 1 to 0 on subsequentattempts
to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and thedata read on the Data Bus D0-D7 is
the addressed memory byte. The device is now
accessible for a new Read or Write operation. The
cycle is finished when two successive Reads yield
the same output data.
I
The Toggle Flag (DQ6) bit is effective after the
fourth Write pulse (for a Program instruction)or
after the sixth Write pulse (for an Erase
instruction).
I
If the byte to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
I
If all the Flash memory sectors selected for
erasure areprotected,theToggle Flag(DQ6)bit
toggles to 0 for about 100
μ
sand then returnsto
the previous addressed byte.
Error Flag (DQ5).
During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. This
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In thecase of Flash memory programming, theEr-
ror Flag (DQ5)bit indicates theattempt to program
a Flashmemory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag (DQ5)bit may also indicate a Time-out condi-
tion while attempting to program a byte.
In caseof an error ina Flashmemory Sector Erase
or ByteProgram cycle, the Flash memory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3).
The Erase
out Flag (DQ3) bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag (DQ3) bit is
reset to 0 after a Sector Erase cycle for a time pe-
riod of 100
μ
s + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag (DQ3) bit is
set to 1.
Time-
Functional Block
FS0-FS7/CSBOOT0-
CSBOOT3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash Memory
V
IH
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Time-
out
X
X
X
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參數(shù)描述
PSD834F2V-15J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-15M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD834F2V-20MI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD835G2-70U 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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