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參數(shù)資料
| 型號： | PSD813FH |
| 英文描述： | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器) |
| 中文描述： | 場可編程微控制器外圍設(shè)備與快閃記憶體（帶閃存的現(xiàn)場可編程微控制器） |
| 文件頁數(shù)： | 82/83頁 |
| 文件大?。?/td> | 369K |
| 代理商： | PSD813FH |
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PSD813FN/FH
Prelimnary
82
Device Operation
(cont.)
Instructions and Commands
(cont.)
J
Sector Erase (SE) Instruction
This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is
written to address 5555h on third cycle after the two coded cycles. The Sector Erase
Confirm command 30h is written on sixth cycle after another two coded cycles. During
the input of the second command an address within the sector to be erased is given
and latched into the memory. Additional Sector Erase confirm commands and sector
addresses can be written subsequently to erase other sectors in parallel, without further
coded cycles. The erase will start after an Erase timeout period of about 100 μs. Thus,
additional Sector Erase commands must be given within this delay. The input of a new
Sector Erase command will restart the timeout period. The status of the internal timer
can be monitored through the level of D3, if D3 is ‘0’ the Sector Erase Command
has been given and the timeout is running, if D3 is ‘1’, the timeout has expired and
the P/E.C. is erasing the sector(s). Before and during Erase timeout, any command
different from 30h will abort the instruction and reset the device to read array mode. It is
not necessary to program the sector with 00h as the P/E.C. will do this automatically
before to erasing to 0FFh. Read operations after the sixth rising edge of WRF or CSF
output the status register status bits.
During the execution of the erase by the P/E.C., the memory accepts only the ES
(Erase Suspend) and RST (Reset) instructions. Data Polling bit D7 returns a ‘0’ while
the erasure is in progress and a ‘1’ when it has completed. The Toggle Bit D6 toggles
during the erase operation. It stops when erase is completed. After completion the
Status Register bit D5 returns ‘1’ if there has been an Erase Failure because erasure
has not completed even after the maximum number of erase cycles have been
executed. In this case, it will be necessary to input a Reset (RST) to the command
interface in order to reset the P/E.C.
J
Program(PG) Instruction
This instruction uses four write cycles. The Program command A0h is written on the
third cycle after two coded cycles. A fourth write operation latches the Address on the
falling edge of WRF or CSF and the Data to be written on its rising edge and starts the
P/E.C. During the execution of the program by the P/E.C. by the P/E.C., the memory
will not accept any instruction. Read operations output the status bits after the
programming has started. Memory programming is made only by writing ‘0’ in place of
‘1’ in a Byte.
J
Erase Suspend (ES) Instruction
The Sector Erase operation may be suspended by this instruction which consists of
writing the command 0B0h without any specific address code. No coded cycles are
required. It allows reading of data from another sector while erase is in progress. Erase
suspend is accepted only during the Sector Erase instruction execution and defaults to
read array mode. Writing this command during Erase timeout will, in addition to
suspending the erase, terminate the timeout. The Toggle Bit D6 stops toggling when
the P/E.C. is suspended. Toggle Bit status must be monitored at an address out of the
sector being erased.
The Toggle Bit will stop toggling between 0.1 μs and 15 μs after the Erase Suspend
(ES) command has been written. The Flash Memory will then automatically set to Read
Memory Array mode. When erase is suspended, Read from sectors being erased will
output invalid data, Read from sector not being erased is valid. During the suspension
the memory will respond only to Erase Resume (ER) and Reset (RST) instructions.
The RST command will definitively abort erasure and result in invalid data in the
sectors being erased.
Appendix A –
Flash Memory
(cont.)
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| PSD813FH-15J | 制造商:WSI 功能描述: |
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| PSD813FN-15J | 制造商:WSI 功能描述: |
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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