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參數(shù)資料
| 型號： | PSD813F4-70M |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 66/103頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | PSD813F4-70M |
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PSD8XXF2/3/4/5
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface block can be enabled
on Port C (see Table 34). All memory blocks (pri-
mary and secondary Flash memory), PLD logic,
and PSD8XXFX Configuration Register bits may
be programmed through the JTAG Serial Interface
block. A blank device can be mounted on a printed
circuit board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD8XXFX (as shipped
from the factory or after erasure), four pins on Port
C are enabled for the basic JTAG signals TMS,
TCK, TDI, and TDO.
See Application Note
AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
JTAG serial command from an external JTAG con-
troller device (such as FlashLINK or Automated
Test Equipment). When the enabling command is
received, TDO becomes an output and the JTAG
channel is fully functional inside the PSD8XXFX.
The same command that enables the JTAG chan-
nel may optionally enable the two additional JTAG
signals, TSTAT and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD8XXFX I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside
the PSD is set by the designer in
the PSDsoft Express Configuration
utility.
This
dedicates the
pins
for JTAG at all times (compliant
with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a
bit at run-time by writing to the
PSD
register,
JTAG
Enable.
This
register
is
located
at
address
CSIOP
+
offset
C7h.
Setting
the
JTAG_ENABLE
bit
in this
register
will enable the pins for JTAG use.
This bit is cleared by a PSD reset
or the microcontroller. See Table
35 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT)
inside the PSD can be used to en-
able
the
JTAG
pins.
This
PT
has
the
reserved
name
JTAGSEL.
Once
defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when
the
Port
C
JTAG
pins
are
multi-
plexed with other I/O signals. It
is
recommended
to
logically
tie
the node JTAGSEL to the JEN\ sig-
nal
on
the
Flashlink
cable
when
multiplexing JTAG signals. See Ap-
plication
Note
1153 for
details.
*/
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft Express). However, Reset (RE-
SET) will prevent or interrupt JTAG operations if
the JTAG enable register is used to enable the
JTAG pins.
The PSD8XXFX supports JTAG In-System-Con-
figuration (ISC) commands, but not Boundary
Scan. The PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Configuration (ISC) com-
mands. A definition of these JTAG In-System-
Configuration (ISC) commands and sequences is
defined in a supplemental document available
from ST. This document is needed only as a refer-
ence for designers who use a FlashLINK to pro-
gram their PSD8XXFX.
Table 34. JTAG Port Signals
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
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