參數(shù)資料
型號(hào)： PSD813390MT
廠(chǎng)商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 1/110頁(yè)
文件大小： 1685K
代理商： PSD813390MT
1/110
August 2004
PSD813F1
Flash In-System Programmable (ISP)
Peripherals for 8-bit MCUs, 5V
FEATURES SUMMARY
DUAL BANK FLASH MEMORIES
–
1 Mbit of Primary Flash Memory (8
Uniform Sectors)
–
256 Kbit Secondary EEPROM (4 Uniform
Sectors)
–
Concurrent operation: read from one
memory while erasing and writing the
other
16 Kbit SRAM (BATTERY-BACKED)
PLD WITH MACROCELLS
–
Over 3,000 Gates Of PLD: DPLD and
CPLD
–
DPLD - User-defined Internal chip-select
decoding
–
CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
27 RECONFIGURABLE I/Os
–
27 individually configurable I/O port pins
that can be used for the following
functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note:
16 of the I/O ports may be
configured as open-drain outputs.
ENHANCED JTAG SERIAL PORT
–
Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
–
Efficient manufacturing allows for easy
product testing and programming
PAGE REGISTER
–
Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
PROGRAMMABLE POWER MANAGEMENT
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Figure 1. Packages
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HIGH ENDURANCE:
–
100,000 Erase/WRITE Cycles of Flash
Memory
–
10,000 Erase/WRITE Cycles of EEPROM
–
1,000 Erase/WRITE Cycles of PLD
–
Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
SINGLE SUPPLY VOLTAGE:
–
5V±10% for 5V
STANDBY CURRENT AS LOW AS 50μA
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PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
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