參數(shù)資料
型號(hào)： PSD613E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁(yè)數(shù)： 2/84頁(yè)
文件大?。?/td> 426K
代理商： PSD613E1
PSD6XX Family
11-2
General
Information
The PSD6XX series of Field Programmable Microcontroller Peripherals combine an
innovative architecture with advanced technology to provide a user-programmable,
high-performance, low-power solution to microcontroller system design. The embedded
input and output Micro
Cells enable efficient implementation of user defined logic
functions that require both software and hardware interaction. The devices eliminate the
need for discrete ‘glue’ logic and allow the development of entire systems using only a few
highly integrated devices.
The PSD6XX family is supported by the Windows-based PSDsoft Development System.
The PSDsoft design flow is shown in Figure 1. The PLD design entry is done using
PSDabel, which creates a minimized logic implementation, and provides logic simulation
of the PLDs. The PSD6XX Bus Interface and I/O Port configuration are entered in
PSDconfiguration.
The PSDcompiler, comprised of a fitter and address translator, generates an object
file from the PSDabel, PSDconfiguration and MCU code files. The object file is then
down loaded to a programmer (MagicPro III, Data I/O, or other third party programmer
for device programming) or to PSDsimulator (PSDsilos III Logic simulator) for device-level
simulation.
Development
System
J
Twenty six individually configurable I/O Port pins. The Ports may be used as MCU I/Os,
PLD I/Os, latched MCU address outputs or special function I/Os. Fifteen I/O port pins
can be configured as open drain outputs.
J
Internal EPROM in densities of 256 Kbit, 512 Kbit and 1 Mbit, configurable in eight
or sixteen-bit widths. The EPROM is divided into eight equal-size blocks, accessible
by user-specified addresses. The access time includes address latching and PLD
decoding. The EPROM includes a low power option.
J
Internal 4 Kbit SRAM that can be configured in eight or sixteen-bit data widths. The
SRAM retains data if power is lost by automatically switching to standby power.
J
A page register expands the microcontroller address space by a factor of sixteen.
J
A security bit prevents copying the PSD6XX configuration and PLD logic as well as
the EPROM contents on device programmers.
J
The programmable Power Management Unit (PMU) supports two separate, low-power
modes allowing operations with as little as 25 μA (at 5V V
CC
). The device can
automatically detect a lack of microcontroller activity and put the PSD into power down
mode.
J
The devices are available in EPROM versions. They are ideal for prototyping and
low-volume production, and in OTP versions for high-volume, low-cost applications.
J
Package choices include 52 pin plastic (J) and ceramic (L) chip carriers.
J
PSD6XX family development is supported by the WSI’s PC based PSDsoft
software
system. The software is MS-Windows
and Windows 95 compatible. The suite
includes PSDabel
(ABEL
), to specify the PLD logic, and an efficient fitter. The tool
also includes the PSDsilosIII simulator from SIMUCAD
. The MagicPro
III programmer
is an engineering development tool and can program any PSD device.
Key Features
(cont.)
Please refer to the revision block at
the end of this document for updated
information.
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相關(guān)代理商/技術(shù)參數(shù)
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