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參數(shù)資料
| 型號： | PSD603E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 9/84頁 |
| 文件大?。?/td> | 426K |
| 代理商： | PSD603E1 |
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PSD6XX Family
11-9
PSD6XX devices consist of several major functional blocks. Figure 2 shows the
architecture of the PSD6XX device family. The functions of each block are described briefly
in the following sections. Many of the blocks perform multiple functions, and are user
configurable.
PLDs
The device contains three PLD blocks each optimized for a different function as shown in
Table 5. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance and ease of design entry.
The Decode PLD (DPLD) is used to decode and generate chip selects for the PSD6XXE1
internal memory, registers and peripheral mode. The External Chip Select PLD (ECSPLD)
is optimized to generate chip selects for devices external to the PSD6XXE1. The General
Purpose PLD (GPLD) can implement user defined logic functions. The DPLD and ECSPLD
have combinatorial outputs while the GPLD has 12 Output Micro
Cells. The PSD6XXE1
also has 23 Input Micro
Cells that can be configured as inputs to the PLD. The PLDs
receive their inputs from the PLD Input bus and are differentiated by their output
destinations, number of product terms, and Micro
Cells.
I/O Ports
The PSD6XXE1 has 26 I/O pins divided among four ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B, C and D can be configured as standard
MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed
address/data busses.
Ports A and B can also be configured as a data port for microcontrollers with a
non-multiplexed bus. In these modes, Port A is connected to D0–7 and Port B to D8–15.
PSD6XXE1
Architectural
Overview
Name
Abbreviation
Inputs
Outputs
Product Terms
Decode PLD
DPLD
63
12
13
External Chip Select PLD
ECSPLD
24
7
7
General PLD
GPLD
63
12
109
Table 5.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD603E1-70L | 制造商:WSI 功能描述: |
| PSD60-A | 制造商:WALL 制造商全稱:Wall Industries,Inc. 功能描述:60 Watt Dual Output AC/DC Power Supply |
| PSD60-B | 制造商:WALL 制造商全稱:Wall Industries,Inc. 功能描述:60 Watt Dual Output AC/DC Power Supply |
| PSD61 | 制造商:POWERSEM 制造商全稱:POWERSEM 功能描述:Three Phase Rectifier Bridges |
| PSD611E1-15J | 制造商:WSI 功能描述: 制造商:WSI 功能描述:32K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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