參數(shù)資料
型號(hào): PSD513B1
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,16K的位的SRAM,40余個(gè)可編程輸入/輸出,通用PLD的有61個(gè)輸入)
文件頁數(shù): 7/25頁
文件大?。?/td> 186K
代理商: PSD513B1
PSD5XX – Application Note 042
4-303
SRAM
PSD503
17 BITS ADDRESS
16 BITS ADDRESS/DATA BUS
CONTROL SIGNALS & INTERRUPT
TIMERS [0:3] OUTPUTS & LOGIC CONTROL BUS
80C186
MICROPROCESSOR
LOGIC FOR
STEPPER
MOTOR
CONTROL
AXIS #1
POWER AMP #1
POWER AMP #2
POWER AMP #3
POWER AMP #4
AXIS #2
AXIS #3
AXIS #4
STEPPER #1
STEPPER #2
STEPPER #3
STEPPER #4
Figure 8. Simplified Block Diagram for the System
Stepper Motor
Clock
Generation
by Using a
PSD5XX
(Cont.)
The output of the PSD5XX interrupt controller is connected to one ot the interrupt inputs
on the 80C186 microprocessor. The PSD5XX interrupt controller interrupts the
microprocessor in response to the timer underflow. In response to this interrupt, the
microprocessor reads the INTERRUPT PRIORTY STATUS REGISTER and updates the
respective timer image register. The output of a timer makes a high to low transition when a
timer count expires.The high to low transition of the timer is inverted and is used to preload
the respective timer from the last image register. In the slewing mode the IMAGE
REGISTER for a timer does not need to be preloaded on each step interrupt. As the timer
count expires the old count will be pre-loaded automatically. Figure 9 shows the logic
configuration for a given axis and Figure 10 shows the *.abl file listing for the preloading
capability of the timers.
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