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參數(shù)資料
| 型號： | PSD512B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 186K |
| 代理商： | PSD512B1 |
PSD5XX – Application Note 042
4-301
Figure 7 shows the programmable PLD (PPLD) macrocell for each counter/timer block
diagram in the PSD5XX. In this design the four 16 bit timers on the PSD5XX are used to
control a four axis stepper motor under microprocessor control. The four 16-bit timers in the
PSD5XX are configured in the pulse mode. The Timers are loaded with a given step count
for the duration of a pulse. When the pulse duration has expired, the logic on the PSD5XX
is programmed such that the respective timer is preloaded with the count from the Image
Registers. By preloading the timer, the step pulse duration will be exact with respect to the
applied clock frequency. The timer clocks are configured to run at 1-MHz. In this case the
preloading time on this system is based on a “one step ahead” stepper motor control. On
the ramp up and ramp down mode each step clock will be preloaded in the image register
because of the step rate changes. When the time for each step has expired the respective
timer automatically preloads the image register in the count register and continues the new
count. In this design the terminal count outputs (TC0 – TC3) of the timers are routed to the
four inputs (INT0– INT3) of the interrupt controller on the PSD5XX device. The timer
outputs are inverted and connected to the timer macrocell outputs MC2TMRx (x = 0 – 3 for
three timers) in the PPLD logic. Figure 8 shows a simplified block diagram for the four axis
stepper motor control.
STEP CLOCKS
RAMP UP
SLEW RATE
RAMP DOWN
MOTOR VELOCITY PROFILE
PROFILE TIME
Figure 6. Typical Trapezoidal Speed Profile
Stepper Motor
Clock
Generation
by Using a
PSD5XX
(Cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD513B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD611E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| PSD601E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| PSD602E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| PSD603E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD512B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD512B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD512B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD512B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD512B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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