參數(shù)資料
型號： PSD501B1-C-90JI
廠商： 意法半導體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場可編程微控制器外圍設備
文件頁數(shù)： 29/153頁
文件大?。?/td> 1036K
代理商： PSD501B1-C-90JI
PSD5XX Famly
26
9.1.3 The PPLD
The Peripheral Programmable Logic Device (PPLD) provides a powerful mechanism for
the user to control the operations of the Counter/Timer and Interrupt Controller. Figure 12 is
the PPLD block diagram. There are six Peripheral Macrocells, four are dedicated to the
Counter/Timer, and two to the Interrupt Controller.
The outputs from the four Peripheral Macrocells, MC2TMR[3:0], are used as
load/store/enable inputs to the Counter/Timer (multiplexed with pin inputs TIMER[3:0]_IN).
The remaining two macrocell outputs (MC2INT[6:7]), together with two other product terms
(PT2INT4, PT2INT5), can generate up to 4 user defined interrupts to the Interrupt
Controller. The watch-dog output of the Timer (WDOG2PLD) and Interrupt Controller
(INTR2PLD) are available as inputs to the ZPLD’s AND ARRAY.
The structure of a Peripheral Macrocell is shown in Figure 13. The cell has two product term
inputs from the AND ARRAY. The user can select the registered or combinatorial output of
the macrocell, as well as the output polarity. The registers are clocked by the CLKIN clock,
and are cleared by the RESET input during power up.
9.1.4 The ZPLDPower Management
The ZPLD implements a Zero Power Mode, which provides considerable power savings
for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the
Power Management Mode Register 0 (PMMR0) has to be turned off.
If none of the 61 inputs to the ZPLD are switching for a time period of 70ns, the ZPLD puts
itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume
normal operation as soon as one or more of the inputs change state.
Two other features of the ZPLD provide additional power savings:
1. Clock Disable:
Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC
power consumption.
2. Product Term Disable:
Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically
for further power savings.
The ZPLD power configuration is described in the Power Management Unit section.
The PSD5XX
Architecture
(cont.)
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相關代理商/技術參數(shù)
參數(shù)描述
PSD501B1C-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 256K 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD501B1-C-90UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD501H 制造商:PACELEADER 制造商全稱:PACELEADER INDUSTRIAL 功能描述:SURFACE MOUNT SCHOTTKY BARRIER DIODES
PSD502B1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD502B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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