參數(shù)資料
型號： PSD501B1-C-90JI
廠商： 意法半導體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場可編程微控制器外圍設備
文件頁數(shù)： 26/153頁
文件大小： 1036K
代理商： PSD501B1-C-90JI
PSD5XX Famly
23
The PSD5XX
Architecture
(cont.)
9.1.2.3 Port E Macrocell Structure
Figure 10 shows the PE Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port E. There are 3 user
programmable global product terms output from the GPLD’s AND ARRAY which are shared
by all the macrocells in Port E:
J
PE.OE
Enable or tri-state Port PE output pins
J
PE.PR
Preset D flip flop in the macrocells
J
PE.RE
Reset/Clear D flip flop in the macrocells
Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip
flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as
the Reset input pin except it is user configurable.
The circuit of a PE Macrocell is shown in Figure 11. There are 4 product terms from the
GPLD’s AND ARRAY as input to the macrocell. Users can select the polarity of the output
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop
J
Combinatorial Output
Select output from OR gate
J
GPLD Input
Use Port E pin as dedicated input
J
GPLD Output
Use Port E pin as dedicated output
J
GPLD I/O
Use Port E pin as bidirectional pin
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback from the
combinatorial output, to possibly expand the number of product terms available to
another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected
to Port E pin, Port E can be configured to perform other user defined I/O functions.
If pins PE0 and PE1 are used as bus control signal inputs (ALE, PSEN/BHE), the
corresponding macrocells' feedbacks are disabled. The bus control signals are
connected to the ZPLD Input Bus.
The two global product terms assigned for asynchronous clear (PE.RE) and preset (PE.PR)
are mainly for proper PE Macrocell initialization.
The macrocell flip-flop can also be cleared during reset by MACRO-RST, if such an option
is chosen. The clock source is always the input clock CLKIN.
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
PSD501B1C-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 256K 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD501B1-C-90UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD501H 制造商:PACELEADER 制造商全稱:PACELEADER INDUSTRIAL 功能描述:SURFACE MOUNT SCHOTTKY BARRIER DIODES
PSD502B1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD502B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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