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參數(shù)資料
| 型號： | PSD501B1-C-70L |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 151/153頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | PSD501B1-C-70L |
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PSD5XX Famly
148
21.0
Process
Change Notice,
October 1, 1998
PSD5XX Functional Change:
A change has been implemented in the most recent silicon that improves the way that the
Image Register is updated. This change only applies to Event Count Mode for counter units
CTU0, CTU1, and CTU3.
Previous PSD5XX Silicon:
The Image Register was not updated with the actual event count upon exiting Freeze
mode. As a result, in certain circumstances, the Image Register may not have reflected the
actual event count. Although an incorrect count may have been read from the Image
Register at a given time, no event counts were ever lost because the microcontroller would
eventually read the correct value in the Image Register on subsequent freeze and read
cycles.
Current PSD5XX Silicon:
The Image register is now automatically updated with the actual count upon exiting the
Freeze mode. This ensures that on the very next freeze and read cycle, the microcontroller
will read the actual count from the Image register. There are two restrictions however:
1. If an event occurs within one timer clock period plus two CLKIN periods after the image
register is unfrozen, then the Image Register will not reflect that event on the very next
freeze and read cycle (timer clock period is defined on page 6-79 of the 1996 PSD data
book). Instead, the event will appear in the Image Register on the subsequent freeze
and read cycle.
2. The time between an unfreeze and the beginning of the next freeze has the same time
constraint as number one. There must be at least one timer clock period plus two CLKIN
periods between the end of one freeze cycle and the beginning of the next. This timing
can be controlled by software design.
To reduce the chance of getting a delayed count in the Image Register due to restriction
number 1, execute a software Load/Store command just prior to freezing and reading the
Image Register to force an update to the Image count.
Backwards Compatibility:
This improvement should have no impact on current designs unless these designs
were compensating for lost events. In such cases, compatibility is dependent on the
compensation method that was used. Please contact WSI at apphelp@wsiusa.com if you
think you have an issue or have any questions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD511B1-C-70L | Low Cost Field Programmable Microcontroller Peripherals |
| PSD501B1-C-70U | Low Cost Field Programmable Microcontroller Peripherals |
| PSD512B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD513B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD611E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD501B1-C-70U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD501B1-C-90JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD501B1C-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 256K 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD501B1-C-90UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD501H | 制造商:PACELEADER 制造商全稱:PACELEADER INDUSTRIAL 功能描述:SURFACE MOUNT SCHOTTKY BARRIER DIODES |
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