- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368224 > PSD413F Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) PDF資料下載
參數(shù)資料
| 型號： | PSD413F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個可編程輸入/輸出，通用PLD的有59個輸入） |
| 文件頁數(shù)： | 89/98頁 |
| 文件大?。?/td> | 365K |
| 代理商： | PSD413F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
PSD413F Family
6-89
ADVANCE INFORMATION
Command
Definitions
(cont.)
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are
followed by writing the “set-up” command. Two more “unlock” write cycles are then followed
by the chip erase command.
The chip erase command should not be used on devices that use sector erase
commands. Likewise, sector erase commands should not be used on devices that
use the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing
the Embedded Erase Algorithm command sequence the device will automatically program
and verify the entire memory for an all zero data pattern prior to electrical erase. The erase
is performed concurrently on all sectors at the same time (see Table 5 “Erase and
Programming Performance” for erase times). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last WRF pulse in the command
sequence and terminates when the data on DQ7 is “1” (see Write Operation Status section)
at which time the device returns to read mode.
Figure 2 illustrates the Embedded Erase Algorithm using typical command strings and bus
operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are
followed by writing the “set-up” command. Two more “unlock” write cycles are then followed
by the sector erase command. The sector address (any address location within the desired
sector) is latched on the falling edge of WRF, while the command (30H) is latched on the
rising edge of WRF. After a time-out of 80 μs from the rising edge of the last sector erase
command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations as
described above. This sequence is followed with writes of the Sector Erase command to
addresses in other sectors desired to be concurrently erased. The time between writes
must be less than 80 μs otherwise that command will not be accepted and erasure will start.
It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written.
A time-out of 80 μs from the rising edge of the last WRF will initiate the execution of the
Sector Erase command(s). If another falling edge of the WRF occurs within the 80 μs
time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer
window is still open, see section DQ3, Sector Erase Timer.) Any command other than
Sector Erase during this period will reset the device to read mode, ignoring the previous
command string. In that case, restart the erase on those sectors and allow them to
complete.
(Refer to the Write Operation Status Section for DQ3, Sector Erase Timer operation).
Loading the sector erase buffer may be done in any sequence and with any number of
sectors (0 to 7).
If the multiple sector erase command is used, multiple sectors should be erased in
groups to ensure that a group of sectors is exposed to the same number of
program/erase cycles. In addition, the chip erase command should not be used on a
device that uses sector erase or multiple sector erase commands.
Sector erase does not require the user to program the device prior to erase. The device
automatically programs all memory locations in the sector(s) to be erased prior to electrical
erase. When erasing a sector or sectors the remaining unselected sectors ane not affected.
The system is not required to provide any controls or timings during these operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD413A2F | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
| PSD4235G2V | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復。