參數(shù)資料
型號： PSD413A2-70U
英文描述： Field-Programmable Peripheral
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 8/123頁
文件大?。?/td> 657K
代理商： PSD413A2-70U
PSD4XX Famly
5
5.0
Integrated
Power
Management
TM
Operation
Upon each address or logic input change to the ZPSD, the device powers up from low
power standby for a short time. Then the ZPSD consumes only the necessary power to
deliver new logic or memory data to its outputs as a response to the input change. After the
new outputs are stable, the ZPSD latches them and automatically reverts back to standby
mode. The I
CC
current flowing during standby mode and during DC operation is identical
and is only a few microamperes.
The ZPSD automatically reduces its DC current drain to these low levels and does not
require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally
forces the ZPSD to standby mode independent of other input transitions.
The only significant power consumption in the ZPSD occurs during AC operation.
The ZPSD contains the first architecture to apply zero power techniques to memory and
logic blocks.
Figure 2 compares ZPSD Zero-power operation to the operation of a discrete solution.
A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and
the generation of an address. The ZPSD detects the address transition and powers up for a
short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the new
values. After finishing these operations, the ZPSD shuts off its internal power, entering
standby mode. The time taken for the entire cycle is less than the ZPSD’s “access time.”
The ZPSD will stay in standby mode if inputs do not change between bus cycles. In an
alternate system implementation using discrete EPROM, SRAM, and other discrete
components, the system will consume operating power during the entire bus cycle. This is
because the chip select inputs on the memory devices are usually active throughout the
entire cycle. The AC power consumption of the ZPLD may be calculated using the
composite frequency of the MCU address and control signals, as well as any other logic
inputs to the ZPLD.
NOTE:
The ZPSD4XX is rated for lower standby current (I
SB
) than the PSD4XX.
ALE
DISCRETE EPROM, SRAM & LOGIC
ADDRESS
EPROM
ACCESS
SRAM
ACCESS
EPROM
ACCESS
I
CC
ZPSD
ZPSD
ZPSD
TIME
Figure 2. Zero-Power Operation vs. Dscrete Implementation
相關(guān)PDF資料
PDF描述
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PSD413A2-90U 400V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA7360SE with Standard Packaging
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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