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參數(shù)資料
| 型號(hào)： | PSD4135G1V-90U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 86/93頁(yè) |
| 文件大小： | 503K |
| 代理商： | PSD4135G1V-90U |
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Preliminary Information
PSD4000 Series
83
Symbol
Parameter
1
Conditions Typical
2
Max
Unit
C
IN
C
OUT
C
VPP
Capacitance (for input pins only)
V
IN
= 0 V
V
OUT
= 0 V
V
PP
= 0 V
4
6
pF
Capacitance (for input/output pins)
8
12
pF
Capacitance (for CNTL2/V
PP
)
18
25
pF
NOTES:
1. These parameters are only sampled and are not 100% tested.
2. Typical values are for T
A
= 25
°
C and nominal supply voltages.
T
A
= 25 °C, f = 1 MHz
14.0
Pin Capacitance
15.0
Figure 34.
AC Testing
Input/Output
Waveform
16.0
Figure 35.
AC Testing
Load Circuit
17.0
Programming
3.0V
0V
TEST POINT
1.5V
DEVICE
UNDER TEST
2.01 V
195
C
L
= 30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
Upon delivery from ST, the PSD4000 device has all bits in the PLDs and memories in the
“
1
”
or high state. The configuration bits are in the
“
0
”
or low state. The code, configuration,
and PLDs logic are loaded through the procedure of programming.
Information for programming the device is available directly from ST. Please contact your
local sales representative. (See the last page.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135G1V-90UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81I | CAP 0.01UF 50V 5% NP0(C0G) SMD-1825 TR-7-PL SN-NIBAR |
| PSD4135G1V-A-12J | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.252"; Container: Bulk; Features: Unmarked |
| PSD4135G1V-A-12JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12M | CAP 0.01UF 100V 10% NP0(C0G) SMD-1825 TR-7-PL SN-NIBAR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G1V-90UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G1V-A-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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