- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368163 > PSD4135F3-B-70B81 (意法半導(dǎo)體) CAP 4700PF 100V 10% NP0(C0G) SMD-1210 TR-7-PL SN-NIBAR PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD4135F3-B-70B81 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP 4700PF 100V 10% NP0(C0G) SMD-1210 TR-7-PL SN-NIBAR |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 28/93頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135F3-B-70B81 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Preliminary Information
PSD4000 Series
25
The
PSD4000
Functional
Blocks
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Protection Register
9.1.1.9.2 Reset Instruction
The Reset instruction consists of one write cycle (see Table 8). It can also be optionally
preceded by the standard two write decoding cycles (writing AAh to AAAh and 55h to
554h).
The Reset instruction must be executed after:
1. Reading the Flash Protection status or Flash ID using the Flash instruction.
2. When an error condition occurs (DQ5 (DQ13) goes high) during a Flash programming
or erase cycle.
The Reset instruction will reset the Flash to normal Read Mode immediately. However, if
there is an error condition (DQ5 (DQ13) goes high), the Flash memory will return to the
Read Mode in 25 μSeconds after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Flash programming or Bulk
Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the
Flash memory to normal Read Mode in 25 μSeconds.
9.1.1.9.3 Reset Pin Input
The reset pulse input from the pin will abort any operation in progress and reset the Flash
memory to Read Mode. When the reset occurs during a programming or erase cycle, the
Flash memory will take up to 25 μSeconds to return to Read Mode. It is recommended that
the reset pulse (except power on reset, see Reset Section) be at least 25 μSeconds such
that the Flash memory will always be ready for the MCU to fetch the boot code after reset
is over.
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Main Flash Sector <i> is write protected.
0 = Main Flash Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_
Bit
*
*
*
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Boot Protection Register
Bit Definitions:
Sec<i>_Prot
Sec<i>_Prot
Security_Bit
1 = Flash Boot Sector <i> is write protected.
0 = Flash Boot Sector <i> is not write protected.
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Table 10. Sector Protection/Security Bit Definition
*:
Not used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135F3-B-70B81I | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 4700pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
| PSD4135F3-B-70J | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70M | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70MI | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 0.047uF; Working Voltage (Vdc)[max]: 25V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135F3-B-70B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F3-B-70MI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。