![](http://datasheet.mmic.net.cn/260000/PSD4135G2_datasheet_15949271/PSD4135G2_37.png)
P
P
3
(INPUTS)
(32)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C,F)
(8)
PGR0 -PGR7
A[15:0]
*
(4)
(3)
PD[3:0] (ALE,CLKIN,CSI)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
8 FLASH MEMORY
SECTOR SELECTS
4 SECONDARY
FLASH MEMORY
SECTOR SELECTS
SRAM SELECT
I/O DECODER
SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
3
F
*
NOTES: 1. The address inputs are A[19:4] in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, C or F.