參數(shù)資料
型號： PSD4135F2V-C-20U
廠商： 意法半導(dǎo)體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù)： 63/93頁
文件大?。?/td> 503K
代理商： PSD4135F2V-C-20U
PSD4000 Series
Preliminary Information
60
The
PSD4000
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD4000 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
V
CC
is steady. During this time period the device loads internal configurations, clears
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD4000 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD4000 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V
CC
is below VLKO.
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 26 shows the timing of the power on and warm reset.
OPERATING LEVEL
POWER ON RESET
V
CC
RESET
tNLNH
–
PO
tOPR
tNLNH-A
tNLNH
tOPR
WARM
RESET
Figure 26. Power On and Warm Reset Timing
9.5.3.3
I/OPin, Register and PLD Status at Reset
Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V
CC
ramps up to operating level. Once the PLD
is active, the state of the outputs are determined by the equations specified in PSDsoft.
相關(guān)PDF資料
PDF描述
PSD4135F2V-C-20UI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70B81I Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 3300pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked
PSD4135F2V-C-70J Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4135F2V-C-20UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-C-70JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
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