參數(shù)資料
型號(hào): PSD411A1-C-90JI
廠商: 意法半導(dǎo)體
英文描述: High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125
中文描述: 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁(yè)數(shù): 75/123頁(yè)
文件大小: 657K
代理商: PSD411A1-C-90JI
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PSD4XX Famly
72
10.0
Page
Register
The PSD4XX has a programmable security bit which offers protection from unauthorized
duplication. When the security bit is set, the contents of the EPROM, the PSD4XX
non-volatile configuration bits and ZPLD data cannot be read by EPROM programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured part can be erased and then
re-programmed.
11.0
Security
Protection
Figure 35. Page Register
DPLD
RS0
GPLD
ZPLD
ES0 – 3
PGR0
PGR1
PGR2
PGR3
R/W
D0
D0 – D3
D1
D2
D3
Q0
Q1
Q2
Q3
PAGE
REG.
RESET
The Page Register is 4 bits wide and consists of four D flip flops.The outputs of the Register
(PGR0 – PGR3) are connected to the input bus of the ZPLD. By including the four outputs
as inputs to the DPLD, the addressing capability of the microcontroller is increased by a
factor of 16.
Figure 37 shows the Page Register block diagram. Inputs to the four flip flops are connected
to data bus D0-D3. The output of the Register can be read by the microcontroller. The
Register can operate as an independent register to the microcontroller if page mode is not
implemented.
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