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| 型號(hào)： | PSD403A2-C-15L |
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| 英文描述： | RECTIFIER FAST-RECOVERY SINGLE 1A 200V 40A-ifsm 0.875V-vf 25ns 2uA-ir SMB 5K/REEL-13 |
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PSD4XX Famly
17
9.1.1.4 Port B Macrocell Structure
Figure 7 shows the PB Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and
MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes
directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin
except it is user configurable.
The circuit of a PB Macrocell is shown in Figure 8. There are 10 product terms from the
GPLDs AND ARRAY as inputs to the macrocell. Users can select the polarity of the output,
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop.
J
Combinatorial Output
Select output from OR gate.
J
GPLD Input
Use Port B pin as dedicated input.
J
GPLD Output
Use Port B pin as dedicated output.
J
GPLD I/O
Use Port B pin as bidirectional pin.
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback from the
combinatorial output, to possibly expand the number of product terms available to
another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected to
a Port B pin, Port B can be configured to perform other user defined I/O functions.
Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and
clock input. The signals are defined as follow:
J
PRESET
Active only if defined by a product term (PBi.PR)
J
CLEAR
Two selectable inputs: Reset input and/or user defined product term (PBi.RE)
J
CLK
Two selectable inputs – CLKIN input or user defined product term (PBi.CLK).
The macrocell is operated in Synchronous Mode if the clock input is CLKIN, and is in
Asynchronous Mode if the clock is a product-term clock defined by the user.
Figure 9 shows the input/output path of a PB macrocell to the Port pin with which it is
associated. If the Port pin is specified as a PB output pin in the PSDsoft, the MUX in the I/O
Port Cell selects the PB Macrocell as an output of the Port pin. The output enable signal to
the buffer in the I/O cell can be controlled by a product term from the AND Array.
If the Port pin is specified as a ZPLD input pin, the MUX in the PB Macrocell selects the
Port input signal to be one of the 61 signals in the ZPLD Input Bus.
9.0
The PSD4XX
Architecture
(cont.)
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