參數(shù)資料
型號(hào): PSD401A2-C-70U
廠商: 意法半導(dǎo)體
英文描述: Low Cost Field Programmable Microcontroller Peripherals
中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù): 85/123頁
文件大?。?/td> 657K
代理商: PSD401A2-C-70U
PSD4XX Famly
82
-70
-90**
-15
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min Max
Min Max
Min Max
Unit
I/O Input or Feedback to
Combinatorial Output
t
PD
Port B, E
25
30
34
Add 10
ns
t
RPD
Registered Input to
Combinatorial Output
(Note 1)
27
32
36
Add 10
ns
t
EA
Input to Output Enable
Any Input
25
28
32
Add 10
ns
t
ER
Input to Output Disable
Any Input
25
28
32
Add 10
ns
t
ARP
Register Clear or Preset
Delay
Any Input
27
30
34
Add 10
ns
t
ARPW
Register Clear or Preset
Pulse Width
Any Input
20
25
29
ns
t
ARD
Array Delay
16
18
22
ns
Combinatorial Delays
(5 V ± 10% Versions)
NOTE:
1. Port A and latched address from ADIO (A0, A1, A8 – A15).
*
*
If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**
The -90 speed is available only on Industrial Temperature Range product.
13.7 AC/DC Parameters – ZPLDTimng Parameters
(5 V ± 10% Versions)
-70
-90**
-15
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
Maximum Frequency
External Feedback
1/(t
S
+ t
CO
)
30.30
27.03
23.81
MHz
Maximum Frequency
Internal Feedback (f
CNT
)
f
MAX
1/(t
S
+t
CO
–10)
43.48
37.04
31.25
MHz
Maximum Frequency
Pipelined Data
1/(t
CH
+ t
CL
)
50.00
41.67
33.33
MHz
t
S
Input Setup Time
Any Input
15
17
20
Add 10
ns
t
H
Input Hold Time
Any Input
0
0
0
0
ns
t
CH
Clock High Time
Clock Input
10
12
15
0
ns
t
CL
Clock Low Time
Clock Input
10
12
15
0
ns
t
CO
Clock to Output Delay
Clock Input
18
20
22
0
ns
t
ARD
Array Delay for Product
Term Expansion
Any Macrocell
16
18
22
0
ns
t
MIN
Minimum Clock Period
t
CH
+ t
CL
20
24
29
0
ns
Synchronous Clock Mode
(5 V ± 10%)
*
*
If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**
The -90 speed is available only on Industrial Temperature Range product.
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