參數(shù)資料
型號: PSD312R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,4位頁寄存器,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,無SRAM,4個(gè)位頁寄存器,19個(gè)可編程的I / O,通用PLD的有16個(gè)輸入)
文件頁數(shù): 21/127頁
文件大小: 682K
代理商: PSD312R
PSD3XX Famly
2-21
SRAM
EPROM
The EPROM has 8 banks of memory. Each bank can be placed in any address location by
programming the PAD. Bank0–Bank7 is selected by PAD outputs ES0–ES7, respectively.
Each PSD3XX device has 16K bits of SRAM (except the PSD3XXR versions which have no
SRAM). Depending on the configuration of the data bus, the SRAM organization can be 2K
x 8 (8-bit data bus) or 1K x 16 (16-bit data bus). The SRAM is selected by the RS0 output of
the PAD.
A16–A19
Inputs
If one or more of the pins PC0, PC1 PC2 and CSI/A19 are configured as inputs, the
configuration bits CADDHLT and CATD define their functionality inside the part. CADDHLT
determines if these inputs are to be latched by the trailing edge of the ALE or AS signal
(CADDHLT = 1), or enabled into the PSD3XX at all times (CADDHLT = 0, transparent
mode). CATD determines whether these lines are high-order address lines, that take part in
the derivation of EPROM select signals inside the chip (CATD = 1), or logic input lines that
have no impact on memory or I/O selections (CATD = 0). Logic input lines typically
participate in the Boolean expressions implemented in the PAD B. Unused input pins
should be tied to V
CC
or GND.
EPROM
Size
EPROM
Architecture
EPROM Bank
Architecture
(8 ea)
Device
x8
x16
x8
x16
PSD301
256Kb
32K x 8
16K x 16
4K x 8
2K x 16
PSD311
256Kb
32K x 8
4K x 8
PSD302
512Kb
64K x 8
32K x 16
8K x 8
4K x 16
PSD312
512Kb
64K x 8
8K x 8
PSD303
1Mb
128K x 8
64K x 16
16K x 8
8K x 16
PSD313
1Mb
128K x 8
16K x 8
PSD304R
2Mb
256K x 8
128K x 16
32K x 8
16K x 8
PSD314R
2Mb
256K x 8
32K x 8
相關(guān)PDF資料
PDF描述
PSD313L Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
PSD314RL Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
PSD301 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入)
PSD302 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
PSD313 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
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