- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368146 > PSD304RL Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD304RL |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，無(wú)的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入） |
| 文件頁(yè)數(shù)： | 26/127頁(yè) |
| 文件大?。?/td> | 682K |
| 代理商： | PSD304RL |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)
PSD3XX Famly
2-26
Component
Signals
Contents
All = 1 (Note 23)
CS0–CS10
PAD
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RS0, ES0 – ES7
n/a
n/a
n/a
n/a
All = 0 (Note 23)
Data register A
Direction register A
Data register B
Direction register B
0
0
0
0
NOTE:
23. All PAD outputs are in a non-active state.
Table 11.
Internal States
During and After
Reset Cycle
Signal
Configuration Mode
Condition
Input
Input
Input
Input
Low
Input
High
Tri-stated
Input
High
AD0/A0–AD7/A7
A8–A15
All
All
I/O
Tracking AD0/A0–AD7
Address outputs A0–A7
I/O
CS7–CS0 CMOS outputs
CS7–CS0 open drain outputs
Address inputs A16–A18
CS8–CS10 CMOS outputs
PA0–PA7)
(Port A)
PB0–PB7
(Port B)
PC0–PC2
(Port C)
Table 10.
Signal States
During Reset
Active
(RESET)
RESET
This is an asynchronous input pin that clears and initializes the PSD3XX. Reset polarity is
programmable (active low or active high). Whenever the PSD3XX reset input is driven
active for at least 100 ns, the chip is reset. The PSD3XX must be reset at power up before
it can be used. Tables 10 and 11 indicate the state of the part during and after reset.
For the PSD3XXL, reset is an asynchronous low signal only. Whenever the reset input is
driven low for at least 500 ns, the chip is reset. After reset becomes high, the chip will be
operational only after an additional 500 ns. See Figure 11. Note that during boot-up, the
part is not automatically reset internally and does require an external reset. Tables 10 and
11 indicate the state of the part during and after reset.
A19/CSI
When configured as CSI, a high on this pin deselects, and powers down, the chip.
A low on this pin puts the chip in normal operational mode. For PSD3XX states during the
power-down mode, see Tables 12 and 13, and Figure 12.
In A19 mode, the pin is an additional input to the PAD. It can be used as an address line
(CADLOG3 = 1) or as a general-purpose logic input (CADLOG3 = 0). A19 can be
configured as ALE dependent or as transparent input (see Table 8). In this mode, the chip
is always enabled.
Control Signals
(Cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD312L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,4位頁(yè)寄存器,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD312R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,4位頁(yè)寄存器,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD313L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD314RL | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD301 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD304RL-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304RL-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304RL-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304RL-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304RL-15U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。