參數(shù)資料
型號(hào)： PSB4851
英文描述： Analog Front End for Sophisticated Answering Machine
中文描述： 模擬前端的精密應(yīng)答機(jī)
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 752K
代理商： PSB4851
PSB 4851
Data Sheet
20
09.99
Figure 2-8 shows the synchronization of a frame by AFEFS. The first clock of a new
frame (T
1
) is indicated by AFEFS switching from low to high before the falling edge of T
1
.
AFEFS may remain high during subsequent cycles up to T
32
.
Figure 2-8
AFE Interface - Frame Start
The data is shifted out with the rising edge of AFECLK and sampled at the falling edge
of AFECLK (figure 2-9).
Figure 2-9
AFE Interface - Data Transfer
If AOPR:OVRE is not set, the channel C
3
is not used by the PSB 4851. All values (C
1
,
C
2
, C
3
:ALS) are transferred MSB first. The data clock (AFECLK) rate is fixed at 6.912
MHz. Table 2-3 shows the clock cycles used for the three channels.
Table 2-3
Clock cycles
Clock Cycles
T
1
-T
16
T
17
-T
32
T
33
-T
40
T
41
-T
864
AFEDD (driven by PSB 4860)
C
1
data
C
2
data
C
3
data
0
AFEDU (driven by PSB 4851)
C
1
data
C
2
data
C
3
data
tristate
AFECLK
AFEFS
T
1
T
2
AFECLK
T
1
T
2
AFEDD
AFEDU
bit 7
bit 6
bit 5
bit 7
bit 6
bit 5
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