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參數(shù)資料
| 型號： | PS12018-A |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | AC MOTOR CONTROLLER, 50 A, DFM36 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大?。?/td> | 539K |
| 代理商： | PS12018-A |
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12018-A
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
parametric
limits
are subject
to change.
UP,VP,WP,UN,VN,WN,Br
FO1,FO2,FO3,CL
CU,CV,CW
GND(Logic)
VDL(5V)
ASIPM
CPU
10k
5.1k
0.1nF
R
0.1nF
on
0
VPN
DC-Bus voltage
Control voltage supply
Boot-strap voltage
N-Side input signal
P-Side input signal
Brake input signal
FO1 output signal
VDB
VCIN(N)
VCIN(P)
VCIN(Br)
FOI
VDH, DL
b)
a)
PWM starts
N-side IGBT Current
N-side FWDi Current
t(hold)
td(read)
Delay time
+ICL
–ICL
on
off
on
off
0
on
off
0
Ref
VCIN
V(hold)
IC
(VS)
VC
VCL
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to VDL voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20
s number of pulses =10 ~ 500 de-
pending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br
→ Un/Vn/Wn → Up/Vp/Wp in that order.
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
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