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參數(shù)資料
| 型號： | PS11012 |
| 元件分類： | 運動控制電子 |
| 英文描述： | AC MOTOR CONTROLLER, 8 A, DFM40 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 539K |
| 代理商： | PS11012 |
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11012
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
200
–200
Analogue output signal
data hold range
1
2
3
4
5
400
300
100
0
–100
–300
–400
0
VC+(200%)
VC0
VC
–(200%)
V
C
(V)
VC+
VC–
min
max
Real load current peak value.(%)(Ic=Io! 2)
VDH=15V
TC=
–20~100C
(Fig. 4)
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
VCH(5
s)
VCH(505
s)
0V
VC
500
s
rCH=
VCH(505
s)-VCH(5s)
VCH(5
s)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5
s delayed point.
0V
Input signal VCIN(p) of each phase upper arm
Input signal VCIN(n) of each phase lower arm
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
Error output FO1
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
SC delay time
Short circuit sensing signal VS
Error output FO1
Gate signal Vo of each phase
upper arm(ASIPM internal)
Input signal VCIN of each phase
upper arm
0V
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PS11013 | 功能描述:MOD IPM 3PHASE IGBT 600V 8A RoHS:否 類別:半導體模塊 >> 功率驅(qū)動器 系列:- 標準包裝:15 系列:SPM® 類型:FET 配置:三相反相器 電流:1.8A 電壓:500V 電壓 - 隔離:1500Vrms 封裝/外殼:23-DIP 模塊 |
| PS11014 | 功能描述:MOD IPM 3PHASE IGBT 600V 15A RoHS:否 類別:半導體模塊 >> 功率驅(qū)動器 系列:- 標準包裝:15 系列:SPM® 類型:FET 配置:三相反相器 電流:1.8A 電壓:500V 電壓 - 隔離:1500Vrms 封裝/外殼:23-DIP 模塊 |
| PS11015 | 功能描述:MOD IPM 3PHASE IGBT 600V 20A RoHS:否 類別:半導體模塊 >> 功率驅(qū)動器 系列:- 標準包裝:15 系列:SPM® 類型:FET 配置:三相反相器 電流:1.8A 電壓:500V 電壓 - 隔離:1500Vrms 封裝/外殼:23-DIP 模塊 |
| PS11016 | 功能描述:MOD IPM 3PHASE IGBT 600V 30A RoHS:否 類別:半導體模塊 >> 功率驅(qū)動器 系列:- 標準包裝:15 系列:SPM® 類型:FET 配置:三相反相器 電流:1.8A 電壓:500V 電壓 - 隔離:1500Vrms 封裝/外殼:23-DIP 模塊 |
| PS11017 | 功能描述:MOD IPM 3PHASE IGBT 600V 50A RoHS:否 類別:半導體模塊 >> 功率驅(qū)動器 系列:- 標準包裝:15 系列:SPM® 類型:FET 配置:三相反相器 電流:1.8A 電壓:500V 電壓 - 隔離:1500Vrms 封裝/外殼:23-DIP 模塊 |
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