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參數(shù)資料
| 型號： | PRODUCT |
| 英文描述： | Product Selection Guide 2002 |
| 中文描述： | 產(chǎn)品選型指南2002 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 1061K |
| 代理商： | PRODUCT |
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LSI LO G IC PRO DUC T SELEC TIO N G UIDE
10
10 independent standard IEEE 802.3
Gigabit Ethernet MACs, each
operating at 10/ 100/ 1000 Mbps
data rates
-10/ 100 half duplex supports
622/ 800 MHz system interface
compliant with OIF-SPI4-2.0
-100% throughput for reception of
back to back packet
-SPI-4 burst control
Supports RGMII and RTBI interface to
Copper and Fiber Transceivers
16/ 32-Bit processor interface to
internal registers, management
counters and microprocessor
-Up to 100 MHz
Independent Receive and Transmit
FIFO’s with Programmable
Watermarks
AutoNegotiates between
10/ 100/ 1000
MIIM management using MDC/ MDIO
Receive/ Transmit FIFO: 16K/ 4K Bytes
IEEE 802.3x compliant Flow Control
Interrupt Capability
Internal/ External Loopback
Automatic CRC Generation and
Checking; Packet Error Discarding
Programable GPIO
Programmable max packet size for
Transmit and Receive Jumbo Packet
(20K Byte)
Programmable IPG for rate control
GBIC interface support
Buffering for back to back packet
frame reception
RMON register set compliance with
RMON, SNMP
RX FIFO
16KB
802.3x FlowContro
10/100/1000 MAC
TX FIFO
4KB
PCS
Encode / Decode
RGMI/RTBI Interface
GMI
TBI
10 MACs)
RX FIFO
16KB
802.3x FlowContro
10/100/1000 MAC
TX FIFO
4KB
PCS
Encode / Decode
RGMI/RTBI Interface
GMI
TBI
CPUInterface
RMON
MIM
GBIC
MIM
GBIC
Packet Buffer Interface Logic (SPI-4)
RGMI / RTBI
Contro
Receive
Transmt
CPUInterface
L28310
10-Port Fast/Ggabt Ethernet
Controler
L28310 Functional Block Diagram
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