MD622P是一種高速12位數字模擬轉換器(DAC)結合書(12渠道2:1)輸入多路復用器。轉換器可以操作在一個采樣率高達4.5Gsps時。數字數據輸入與芯片上的LVDS 100歐姆電阻終止。后48對微分數據輸入的多路復用的2倍速度,12高速數據位是閂鎖和編碼DAC輸出級。DAC的模擬輸出在正常握模式之間選擇(1日尼奎斯特樂隊)或歸零模式(第一,第二和第三尼奎斯特樂隊)操作?;パa輸出可用50-?輸出終端。Divided-by-4時鐘LVDS輸出和采樣階段選擇(SEL1和SEL2)提供緩解抽樣階段的定位相對于輸入數據。除以2鐘LVDS輸出還提供。重置功能為系統(tǒng)提供應用程序需要從多個MD622P輸出的同步。
MD622P is a high-speed 12-bit Digital to Analog Converter (DAC) integrated with a 24:12 (12 channels of 2:1) input multiplexer. The converter can be operated at a sampling rate up to 4.5 Gsps. The digital data inputs are LVDS with on-chip 100 ohm termination resistors. After the 48 pairs of differential data inputs were multiplexed up to 2 times of speed, the 12 high speed data bits are latched and encoded to drive DAC output stage. The analog outputs of DAC can be selected between Normal-Hold mode (for the 1st Nyquist band ) or Return-to-Zero mode (for the 1st, 2nd and 3rd Nyquist band) operation. Complementary outputs are available with 50-? output back terminations. Divided-by-4 clock LVDS outputs and sampling phase selection (SEL1 and SEL2) are provided to ease the alignment of sampling phase relative to the input data. Divided-by-2 clock LVDS outputs are also provided. A RESET function is provided for system applICations which need to synchronize the outputs from multiple MD622P’s.
特性
12位DAC > 4-GSPS利率決議
DAC模擬輸出格式可以選擇之間正常握(NH)模式或歸零(RZ)模式
每個輸入2:1復用率DAC
SFDR比-50 dBc
輔以50-?輸出終端
互補除以2 LVDS輸出數據同步
變量400 ~ 800 mVPP單端輸出擺動
芯片上的每個微分100歐姆之間終止
LVDS輸入數據和復位
QFN 10 x10 88 l包墊
應用程序
生成任意波形
雷達/激光雷達設計和測試
軟件定義無線電
電子戰(zhàn)
無線基站
射頻信號源的一代
WLAN測試
高級通信調節(jié)
深圳市立維創(chuàng)展科技有限公司
雷麗芳 (銷售工程師)
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