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參數(shù)資料
| 型號(hào)： | PR31700 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit RISC Microprocessor(32位 RISC微處理器) |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, LQFP-208 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 378K |
| 代理商： | PR31700 |
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Philips Semiconductors
Preliminary specification
PR31700
32-bit RISC microprocessor
1998 May 13
11
NAME
FUNCTIONS
I/O
IROUT
O
This pin is the UART transmit signal from the UART B module or the Consumer IR output signal if
Consumer IR mode is enabled.
IRIN
I
This pin is the UART receive signal to the UART B module.
RXPWR
O
This pin is the receiver power output control signal to the external communication IR analog circuitry.
CARDET
I
This pin is the carrier detect input signal from the external communication IR analog circuitry.
NAME
I/O
FUNCTIONS
Video Pins
FRAME
O
This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by
the LCD to return it’s pointers to the top of the display. The Video Module asserts FRAME after all the lines
of the LCD have been shifted and transferred, producing a full frame of display.
DF
O
This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC
voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to
turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to
toggle every programmable number of LOAD signals.
LOAD
O
This pin is the line synchronization pulse signal between the Video Module and the LCD, and is used by the
LCD to transfer the contents of it’s horizontal line shift register to the LCD panel for display. The Video
Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD.
CP
O
This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and
sampled by the LCD on the falling edge of CP.
VDAT(3:0)
O
These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit non-split
displays. For 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit
data into the desired 8 parallel data lines needed for the LCD.
DISPON
O
This pin is the display-on enable signal for the LCD.
VIDDONE
O
This pin is used to externally synchronize events to periods whenthe vido is not shifting.
NAME
I/O
FUNCTIONS
Endian Pin
ENDIAN
I
This pin is used to select the endianess of the PR31700. The ”1” level input sets the endianess to the big
endian, while the ”0” level input tot he little endian.
NAME
I/O
FUNCTIONS
Test Pins
TESTSIU
I
This pin allows external logic to initiate read or write transactions to PR31700 registers. The TESTSIU
mode is enabled by toggling this signal after the device has powered up. Once the function is enabled, if the
TESTSIU pin is high when the bus is arbitrated (using /DREQ and /DGRNT), then external logic can initiate
read and write transactions to PR31700 registers. This pin is used for debugging purposes only.
TESTCPU
I
This pin allows numerous internal CPU core signals to be brought to external PR31700 pins, in place of the
normal signals assigned to these pins. The CPU core signals assigned to their respective pins during
TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled by asserting this TESTCPU
signal, and this function is provided for generating test vectors for the CPU core. This pin is used for
debugging purposes only.
TESTIN
I
This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only.
VIDDONE
O
This signal is used to synchronize UCB1200 to read touchscreen input, when there is no video data shifted
into LCD panel.
NAME
I/O
FUNCTIONS
Spare Pins
NC5–1
No
Connect
These pins are reserved for future use and should be left unconnected.
RSRV1
I
These pins are reserved for future use and should be connected to ground.
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