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參數資料
| 型號： | PPC7457RX600NB |
| 廠商： | Motorola, Inc. |
| 英文描述： | PPC7457RX1000NB |
| 中文描述： | PPC7457RX1000NB |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 280K |
| 代理商： | PPC7457RX600NB |
MOTOROLA
MPC7457 Part Number Speci
fi
cation for the MPC74x7RXnnnnNx Series
For More Information On This Product,
Go to: www.freescale.com
7
General Parameters
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
t
KHARPZ
—
2
t
SYSCLK
3, 5
6, 7
Notes:
1. All input speci
fi
cations are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the input SYSCLK. All output speci
fi
cations are measured from the midpoint of the rising edge of SYSCLK to the
midpoint of the signal in question. All output timings assume a purely resistive 50-
MPC7457 RISC Microprocessor Hardware Specifications)
time-of-
fl
ight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing speci
fi
cations herein follows the pattern of t
t
(reference)(state)(signal)(state)
for outputs. For example, t
IVKH
(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).
3. t
SYSCLK
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then
precharged high before returning to high impedance, as shown in Figure 6 in the
Hardware Specifications
. The nominal precharge width for TS is 0.5
t
SYSCLK
period, to ensure that another master asserting TS on the following clock will not contend with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge. The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the
fi
rst clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 t
SYSCLK
; that is, it should be high impedance, as shown in Figure 6 in the
Hardware Specifications,
before the
fi
rst opportunity for another master to assert ARTRY. Output valid and output
hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of
TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for
up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width
for SHD0 and SHD1 is 1.0 t
SYSCLK
. The edges of the precharge vary depending on the programmed ratio of core
to bus (PLL con
fi
gurations).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
parameters represent the input setup and hold times for each sample. These values are guaranteed by design and
not tested. These inputs must remain stable after the second sample. See Figure 5 in the
Microprocessor Hardware Specifications
for sample timing.
load (see Figure 4 in the
. Input and output timings are measured at the pin;
(signal)(state)(reference)(state)
for inputs and
symbolizes the time input signals (I) reach the valid state
KHOV
symbolizes the
MPC7457 RISC Microprocessor
, that is, less than the minimum
×
t
SYSCLK
MPC7457 RISC Microprocessor
MPC7457 RISC
Table 9. Processor Bus AC Timing Speci
fi
cations
At recommended operating conditions. See Table 4.
1
(continued)
Parameter
Symbol
2
All Speed Grades
Unit
Notes
Min
Max
F
Freescale Semiconductor, Inc.
n
.
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