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參數資料
型號: PPC5605BCLU48
廠商: Freescale Semiconductor
文件頁數: 95/112頁
文件大?。?/td> 0K
描述: MCU 32BIT 768K 48MHZ
標準包裝: 40
系列: MPC56xx Qorivva
核心處理器: e200z0h
芯體尺寸: 32-位
速度: 48MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數: 149
程序存儲器容量: 768KB(768K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 16
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數據轉換器: A/D 29x10b,5x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-LQFP
包裝: 托盤
Electrical characteristics
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
83
IINJ
SR — Input current Injection
Current
injection on
one ADC_1
input, different
from the
converted one
VDD = 3.3 V ± 10%
–5
5
mA
VDD = 5.0 V ± 10%
–5
5
|INLP |
CC T Absolute integral nonlinearity –
Precise channels
No overload
1
3
LSB
|INLX |
CC T Absolute integral nonlinearity –
Extended channels
No overload
1.5
5
LSB
|DNL |
CC T Absolute differential
nonlinearity
No overload
0.5
1
LSB
|EO |
CC T Absolute offset error
——
2
LSB
|EG |
CC T Absolute gain error
——
2
LSB
TUEP7
CC P Total unadjusted error for
precise channels, input only
pins
Without current injection
–6
6
LSB
T
With current injection
–8
8
TUEX7
CC T Total unadjusted error for
extended channel
Without current injection
–10
10
LSB
T
With current injection
–12
12
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2 Analog and digital V
SS must be common (to be tied together externally).
3 V
AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4 During the sampling time the input capacitance C
S can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end
of the sampling time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for
the sampling clock tADC1_S depend on programming.
5 This parameter does not include the sampling time t
ADC1_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
6 Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by
internal divider by 2.
7 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 45. ADC_1 conversion characteristics (12-bit ADC_1) (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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