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參數(shù)資料
| 型號： | PPC440SP-RFC667C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 83/85頁 |
| 文件大小： | 615K |
| 代理商： | PPC440SP-RFC667C |
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PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
83
Initialization
The PPC440SP provides an option for setting initial parameters based on default values or by reading them from a
serial “bootstrap” ROM attached to the IIC0 bus. These options are defined by strapping on three external pins
(see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440SP start-up. The actual capture instant is the nearest SysClk edge before the
deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. They are used for strap functions only during reset. Following
reset they are used for normal functions.
Figure 21 lists the strapping pins along with their functions and strapping options:
Serial Bootstrap ROM
During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In
this case, at the de-assertion of SysReset, the PPC440SP sequentially reads up to 32 bytes from the ROM device
on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly.
The initialization settings and their default values are described in detail in the
PPC440SP Embedded Processor
User’s Manual
.
Table 21. Strapping Pin Assignments
Function
Option
Pin Strapping
Bit 0
A08
(UART0_DCD)
Bit 1
C11
(UART0_DSR)
Bit2
C09
(UART0_CTS)
Serial Bootstrap ROM is disabled (Bit 0 off).
Refer to the IIC Bootstrap Controller chapter in the
PPC440SP Embedded Processor User’s Manual
for details.
Boot from EBC
0
0
Boot from PCI
0
1
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading
128 bits
from the Bootstrap ROM.
0x54
1
0
0
0x50
1
1
0
Serial Bootstrap ROM is enabled (Bit 0 on).
The options being selected are the IIC0 slave
address that responds with strapping data and
reading
256 bits
from the Bootstrap ROM.
0x54
1
0
1
0x50
1
1
1
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