參數(shù)資料
型號： PPC440SP-RFC667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁數(shù)： 11/85頁
文件大?。?/td> 615K
代理商： PPC440SP-RFC667C
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
11
PCI Power Management Version 1.1
PCI arbitration function with PCI-X Mode 2 support (optional)
PCI register set addressable both from on-chip processor and PCI device sides
Ability to boot from PCI-X bus memory
Error tracking/status
Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (Type 0 and Type 1)
– Single beat special cycles
PCI-X initialization sequence support (frequency & mode determination)
Support for unexpected split completions
Outbound transaction split discard timers
Vital Product Data (VPD) support
PCI-to-PCI opaque bridge
DDR1/DDR2 SDRAM Memory Controller
The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete
devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The
DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-
speed 1KB FIFO buffers.
Features include:
Registered and non-registered industry standard DIMMs
DDR1 266-333-400
DDR2 400-533-667
64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
5.32GB/s peak bandwidth for the 64-bit interface
2.66GB/s peak bandwidth for the 32-bit interface
Two chip (bank) select signals supporting two external banks
CAS latencies of 2, 3, 4, 5, 6, and 7 supported
Page mode accesses (up to 32 open pages) with configurable paging policy
Look-ahead request queue with programmable depth of four commands.
Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
Up to 4GB in two external banks
Programmable address mapping and timing
Hardware and software initiated self-refresh
Sync DRAM configuration by means of mode register and extended mode register set commands
Power management (self-refresh, suspend, sleep)
Low Latency & High Bandwidth PLB ports
Selectable PLB read response (immediate or deferred)
Programmable Low Latency & High Bandwidth arbitration schemes
High Bandwidth port has four 1KB read buffers and two1KB write buffers
Low Latency port has four 128B read buffers and two 128B write buffers
External Peripheral Bus Controller (EBC)
Features include:
Support 2MB Boot ROM
Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported
Burst and non-burst devices
8-bit data bus
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