參數(shù)資料
型號(hào)： PPC440SP-ANC533C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 59/85頁(yè)
文件大?。?/td> 615K
代理商： PPC440SP-ANC533C
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
59
Ethernet Interface
EMCCD
Collision detection.
I
3.3V LVTTL
EMCCrS
Carrier sense.
I
3.3V LVTTL
EMCMDClk
Management data clock.
O
3.3V LVTTL
EMCMDIO
Transfer command and status information between MII
and PHY.
I/O
3.3V LVTTL
EMCRxD0:7
Receive data.
I
3.3V LVTTL
EMCRxDV
Receive data valid.
I
3.3V LVTTL
EMCRxErr
Receive error.
I
3.3V LVTTL
EMCRxClk
Receive clock.
I
3.3V LVTTL
EMCRefClk
Reference clock.
I
3.3V LVTTL
EMCTxClk
Transmit clock.
I
3.3V LVTTL
EMCGTxClk
Ethernet gigabit transmit clock.
O
3.3V LVTTL
EMCTxD0:7
Transmit data.
O
3.3V LVTTL
EMCTxEn
Transmit data enabled.
O
3.3V LVTTL
EMCTxErr,
Transmit error.
O
3.3V LVTTL
External Slave Peripheral Interface
PerAddr00:23
Peripheral address bus.
Note:
PerAddr00 is the most significant bit (msb).
O
3.3V LVTTL
1
PerBE0
External peripheral data bus byte enable.
O
3.3V LVTTL
1
PerBLast
Used by the peripheral controller to indicates the last
transfer of a memory access.
O
3.3V LVTTL
PerCS0:2
External peripheral device select.
O
3.3V LVTTL
PerData0:7
Peripheral data bus.
Note:
PerData0 is the most significant bit (msb).
I/O
3.3V LVTTL
1
PerOE
Used by peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440SP is the bus master, it enables the selected
device to drive the bus.
O
3.3V LVTTL
PerPar0
External peripheral data bus byte parity.
I/O
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to
transfer data.
I
3.3V LVTTL
PerR/W
Used as output by the peripheral controller. High
indicates a read from memory, low indicates a write to
memory.
O
3.3V LVTTL
1
PerWE
Write Enable.
O
3.3V LVTTL
PerClk
Peripheral clock used by synchronous peripheral slaves.
O
3.3V LVTTL
PerErr
External error used as an input to record external slave
peripheral errors.
I
3.3V LVTTL
1, 5
Table 6. Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
PPC440SP-ANC667C PowerPC 440SP Embedded Processor
PPC440SP-RFC533C PowerPC 440SP Embedded Processor
PPC440SP-RFC667C PowerPC 440SP Embedded Processor
PPC440SP-RNC533C PowerPC 440SP Embedded Processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC440SP-ANC667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor
PPC440SPE 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-3GA533C 制造商:AppliedMicro 功能描述:
PPC440SPE-3GA667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-3NA533C 制造商:AppliedMicro 功能描述:
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