- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄368096 > PPC440GX-3RF800CZ (APPLIEDMICRO INC) Power PC 440GX Embedded Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | PPC440GX-3RF800CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GX Embedded Processor |
| 中文描述： | 32-BIT, 800 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, ROHS COMPLIANT, CERAMIC, FBGA-552 |
| 文件頁(yè)數(shù)： | 56/93頁(yè) |
| 文件大小： | 794K |
| 代理商： | PPC440GX-3RF800CZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
440GX – Power PC 440GX Embedded Processor
56
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
System Interface
SysClk
Main system clock input.
Clock
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
O
3.3V LVTTL
SysReset
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
During chip power-up, this signal must be low from the start of V
DD
ramp-up until at least 16 SysClk cycles after V
DD
is stable.
I/O
3.3V LVTTL
1, 2
TmrClk
Processor timer external input clock.
I
3.3V LVTTL
Halt
Halt from external debugger.
I
3.3V LVTTL
1, 4
GPIO00:31
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
I/O
3.3V LVTTL
TestEn
Test Enable.
I
3.3V tolerant
2.5V CMOS
3
RcvrInh
Receiver Inhibit. Active only when TestEn is active.
I
3.3V LVTTL
RefVEn
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
I
3.3V LVTTL
w/pull-down
DrvrInh2
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
I
3.3V LVTTL
w/pull-up
2
Signal Functional Description
(Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440GX-3CC533S | Power PC 440GX Embedded Processor |
| PPC440GX-3CC667S | Power PC 440GX Embedded Processor |
| PPC440GX-3CF400C | Power PC 440GX Embedded Processor |
| PPC440GX-3CF533C | Power PC 440GX Embedded Processor |
| PPC440GX-3CF533CZ | Power PC 440GX Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SP | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-3FB533C | 制造商:AMCC 功能描述: 制造商:AppliedMicro 功能描述: |
| PPC440SP-AFC533C | 制造商:AMCC 功能描述:AMCPPC440SP-AFC533C POWER PC |
| PPC440SP-AFC667C | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-ANC533C | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。