參數(shù)資料
型號: PPC440GX-3CF667CZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: Power PC 440GX Embedded Processor
中文描述: 32-BIT, 667 MHz, RISC PROCESSOR, CBGA552
封裝: 25 X 25 MM, CERAMIC, FBGA-552
文件頁數(shù): 73/93頁
文件大?。?/td> 794K
代理商: PPC440GX-3CF667CZ
440GX – Power PC 440GX Embedded Processor
AMCC
73
Revision 1.15 – August 30, 2007
Data Sheet
Ethernet RGMII Interface
GMC0RxClk
na
na
na
na
na
na
1,
async
GMC0RxCtl
1
1
na
na
na
na
GMC0RxClk
4, 5
GMC0RxD0:3
1
1
na
na
5.1
6.8
GMC0RxClk
4, 5
GMC0TxClk
na
na
na
na
5.1
6.8
1,
async
GMC0TxCtl
na
na
0.5
3.5
5.1
6.8
GMC0TxClk
4, 5
GMC0TxD0:3
na
na
0.5
3.5
5.1
6.8
GMC0TxClk
4, 5
GMC1RxClk
na
na
na
na
na
na
1,
async
GMC1RxCtl
1
1
na
na
na
na
GMC1RxClk
4, 5
GMC1RxD0:3
1
1
na
na
5.1
6.8
GMC1RxClk
4, 5
GMC1TxClk
na
na
na
na
5.1
6.8
1,
async
GMC1TxCtl
na
na
0.5
3.5
5.1
6.8
GMC1TxClk
4, 5
GMC1TxD0:3
na
na
0.5
3.5
5.1
6.8
GMC1TxClk
4, 5
GMCRefClk
na
na
na
na
na
na
async
Ethernet TBI Interface
TBIRxClk0
na
na
na
na
na
na
1,
async
TBIRxClk1
na
na
na
na
na
na
1,
async
TBIRxD0:9
2.5
1.5
na
na
5.1
6.8
TBIRxClkx
TBITxClk
na
na
na
na
na
na
1,
async
TBITxD0:9
na
na
6
1
5.1
6.8
TBITxClk
I/O Specifications—All Speeds
(Sheet 4 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O H
(minimum)
I/O L
(minimum)
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